Data Communication Interface for Low Power Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In low power systems, microprocessors consume significant power due to frequent switching between active and inactive states during data collection from peripheral devices, leading to increased power consumption and 'false starts' when data does not meet preconditions for processing.
Innovation Solution
An improved data communication interface that offloads data collection and processing from the microprocessor, using flow control logic blocks and data processing logic blocks to maintain a single communication session with sensors, allowing the microprocessor to remain in a sleep mode and reducing power consumption by verifying data preconditions before waking the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the microprocessor frequently switches between active and inactive states during data collection, then the system can respond to data availability, but power consumption increases significantly
Solution Approach 1:
The flow control logic block performs preliminary actions by automatically reading sensor data and verifying preconditions before the microprocessor wakes up. This allows the microprocessor to remain in sleep mode longer, reducing power consumption while ensuring data is ready for processing when the processor becomes active.
Solution Approach 2:
The flow control logic block acts as an intermediary between the sensor and the microprocessor. It handles data collection and precondition verification, allowing the microprocessor to stay inactive while still monitoring data availability through interrupt signals.
2Loss of time
If the microprocessor processes data immediately upon collection, then processing can begin without delay, but the processor cannot remain in sleep mode
Solution Approach 1:
The flow control logic block performs preliminary data reading and precondition verification before the microprocessor wakes up. This eliminates processing delays because data is already prepared and ready when the processor becomes active, while the processor itself consumes minimal power during the data collection phase.
3Reliability
If the microprocessor verifies data preconditions, then false starts are reduced, but the processor must be active during verification
Solution Approach 1:
The flow control logic block serves as an intermediary that performs precondition verification on behalf of the microprocessor. It checks whether collected data meets required preconditions and only triggers a processor wake-up when verification succeeds, thereby reducing false starts and improving reliability while keeping the processor in sleep mode during verification.
4Device complexity
If multiple communication sessions are used to read sensor data, then data can be collected in smaller batches, but communication overhead increases
Solution Approach 1:
The flow control logic block merges multiple data reading operations into a single communication session. It reads a predetermined number of sensor values continuously without breaking the communication connection, thereby reducing communication overhead and minimizing the time the microprocessor needs to remain active.
Data Source
AI summary
Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).