Data Inversion Register for DRAM Testing
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Solution Overview
Problem
Manufacturing testing of wide I/O DRAM circuits is challenging due to the lack of pattern capability in existing data compression test modes, which fail to effectively exercise the full memory array and data path, and conventional data path circuits cannot write data stripes from a single data input signal.
Innovation Solution
The data inversion register technique inverts data input signals in a predetermined pattern to maximize the probability of identifying failures, allowing for reduced data inputs and outputs, and enables the creation of 'worst-case' test patterns for I/O circuitry and memory arrays, with control over which data bits are inverted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data compression test modes are used for wide I/O DRAM circuits, then testing complexity is reduced, but pattern capability is lost and full memory array and data path cannot be exercised
Solution Approach 1:
The patent segments the data inversion function by allowing selective inversion of specific data bits based on predetermined patterns (e.g., even/odd bits, 1-of-8 bits). This segmentation enables comprehensive testing of different memory array regions and data paths while maintaining manageable test complexity through systematic bit selection and inversion strategies.
2Device complexity
If conventional data path circuits are used, then circuit simplicity is maintained, but capability to write data stripes from a single data input signal is lost
Solution Approach 1:
The patent implements a universal data inversion mechanism that can operate with a single data input signal to generate multiple different data stripe patterns. By controlling which bits are inverted according to predetermined patterns, the same simple circuit structure achieves the ability to write various data stripes, making the circuit multi-functional without increasing complexity.
3Reliability
If more data inputs are supplied to DRAM for comprehensive testing, then testing thoroughness is improved, but number of data inputs and outputs increases
Solution Approach 1:
Instead of increasing the number of data inputs to achieve comprehensive testing, the patent inverts selected data bits from a reduced set of inputs according to predetermined patterns. This inversion technique generates diverse test patterns from fewer inputs, maintaining testing thoroughness while reducing the number of required data inputs and outputs.
Data Source
AI summary
A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.