DRAM Bank Interleave Optimization via Data Kind Address Mapping
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Solution Overview
Problem
Conventional graphics processing units face performance bottlenecks due to memory access hot spots and bank conflicts in DRAM, particularly when accessing 2D data that exhibits localized access patterns, leading to inefficient memory usage and reduced system performance.
Innovation Solution
A method is introduced that translates virtual addresses to physical addresses using data kind bits to optimize the mapping process, reducing bank conflicts and memory access hot spots by modifying the mapping from a linear physical address space to a DRAM physical address space, allowing for improved bank interleaving and access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential bytes in memory are interleaved across multiple DRAM devices to enable parallel access, then memory bandwidth is improved, but memory access hot spots and bank conflicts occur when accessing 2D data with localized access patterns
Solution Approach 1:
The patent applies local quality by using data kind bits to identify different types of data (e.g., 2D textured data vs. other data) and applying different address mapping strategies selectively. For 2D textured data, a modified mapping process is used that distributes accesses more evenly across banks, while other data types use conventional mapping. This resolves the contradiction by optimizing for local access patterns where needed without sacrificing overall memory bandwidth for other data types.
Solution Approach 2:
The patent changes the address mapping parameters dynamically based on data kind. By modifying how physical addresses are mapped to DRAM banks and devices according to the data type, the system can avoid bank conflicts for 2D data while maintaining efficient parallel access for other data types. This parameter change approach allows the system to adapt the memory access strategy to match the access pattern characteristics of different data kinds.
2Productivity
If bank interleaving is used to hide activation latency through parallel bank operations, then memory efficiency is improved, but sequential requests to different rows within the same bank serialize the activate operations
Solution Approach 1:
The patent addresses this contradiction by modifying the address mapping to distribute sequential 2D data accesses across different banks in a way that exploits the bank dimension more effectively. By changing how row addresses map to bank selections, the system can ensure that sequential row accesses target different banks, allowing activation latency to be hidden through parallel operations rather than serializing the activate sequence.
3Device complexity
If a conventional linear physical address space mapping is used, then address translation is simple, but it creates access hot spots and bank conflicts for 2D data with localized access patterns
Solution Approach 1:
The patent introduces dynamics by making the address mapping adaptive rather than static. The data kind bits determine which mapping strategy is applied, allowing the system to dynamically switch between conventional linear mapping and modified mapping approaches. This dynamic adaptation enables the system to avoid bank conflicts for 2D data while maintaining simple conventional mapping for other data types, thus resolving the contradiction between simplicity and performance.
Data Source
AI summary
Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table entry that specifies the physical address of the virtual page in linear physical address space. The page table entry also includes a data kind field that is used to guide and optimize the mapping process from the linear physical address space to the DRAM physical address space, which is used to directly access one or more DRAM. The DRAM physical address space includes a row, bank and column address. The data kind field is also used to optimize the starting partition number and partition interleave pattern that defines the organization of the selected physical page of memory within the DRAM memory system.