Data Latch Circuit Layout Using AOI22/OAI22 Cells
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Solution Overview
Problem
Standard cell libraries with limited first metal traces face challenges in implementing clocked data latches due to the impossibility of cutting polygate rails and connecting to both PMOS and NMOS in the same Poly track, leading to active polygate rails being cut, which negatively impacts circuit performance by requiring dummy devices.
Innovation Solution
The implementation of a data latch (DLATCH) circuit using combinatorial gates corresponding to AOI22 or OAI22 cells, which eliminates the need for cross-coupled clock signals and dummy devices, allowing for a more compact layout with fewer polygate rails and reduced delay skew, enabling better layout design and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clocked data latch designs with cross coupled clock signals are used, then the latch functionality is achieved, but active polygate rails must be cut requiring dummy devices that negatively impact circuit performance
Solution Approach 1:
The patent extracts and eliminates the cross-coupled clock signals from the latch circuit, using instead a single-phase clock signal combined with combinatorial logic gates (AOI22 or OAI22 cells) to achieve the same latch functionality without requiring polygate rail cuts and dummy devices
Solution Approach 2:
The patent changes the clock signal parameter from cross-coupled multi-phase signals to a single-phase clock signal, and changes the logic structure from traditional latch elements to combinatorial gates, thereby eliminating the need for dummy devices while maintaining functionality
2Ease of manufacture
If standard cell library architecture with limited first metal traces is used, then manufacturing constraints are met, but polygate rails must be cut reducing design flexibility and performance
Solution Approach 1:
Instead of cutting polygate rails to accommodate limited first metal traces, the patent inverts the approach by using combinatorial gates with single-phase clocking that naturally fit within the standard cell architecture without requiring rail cuts, thus maintaining both manufacturability and design simplicity
3Manufacturing precision
If dummy devices are added to compensate for cut polygate rails, then design rules are met, but delay skew increases and performance deteriorates
Solution Approach 1:
The patent converts the harmful effect of polygate rail cuts into a benefit by eliminating the need for dummy devices entirely through the use of combinatorial gates with single-phase clocking, thereby simultaneously achieving design rule compliance and reduced delay skew
Data Source
AI summary
The disclosed method of operation for a data latch (DLATCH) circuit may include receiving, by an input component of the DLATCH circuit, an input signal. The method may additionally include storing, by a combinatorial gate of the DLATCH circuit, a state of the input signal, wherein the combinatorial gate corresponds to at least one of an AND-OR-inverted (AOI22) cell or an OR-AND-inverted (OAI22) cell. The method may further include providing an output signal, by an output component of the DLATCH circuit, wherein the output signal has the state stored by the combinatorial gate. Various other methods, systems, and circuits are also disclosed.