Data Line Driving Circuit Segmentation for Display Uniformity
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Solution Overview
Problem
Conventional time division drive techniques for display apparatuses using amorphous TFTs suffer from display unevenness due to high coupling capacitance between data lines, leading to undesirable signal values and increased electric power consumption, chip area, and reduced contrast.
Innovation Solution
A data line driving circuit with alternately arranged first and second data lines, each connected to separate buffers via switch circuits, allowing for controlled ON periods to minimize coupling capacitance and reduce display unevenness, while maintaining efficient power usage and compact chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pitch between data lines is narrowed to reduce chip area, then the chip area decreases, but the coupling capacitance between data lines increases causing display unevenness
Solution Approach 1:
The patent divides data lines into two separate groups (first data lines and second data lines) that are alternately arranged. Each group is driven by separate buffer circuits with independent control, allowing the coupling capacitance between groups to be utilized beneficially rather than being a harmful interference.
Solution Approach 2:
The patent changes the control parameters by independently controlling the ON periods of the two sets of buffer circuits. By adjusting the timing and duration of signal output from each buffer circuit, the patent optimizes the utilization of coupling capacitance to reduce display unevenness while maintaining narrow pitch between data lines.
2Use of energy by stationary object
If time division drive is used to reduce buffer number, then electric power consumption and chip area decrease, but coupling capacitance between adjacent data lines causes signal interference
Solution Approach 1:
The patent segments the data lines into two interleaved groups and assigns separate buffer circuits to each group. This segmentation allows independent control of signal timing for adjacent data lines, enabling the system to maintain low power consumption through time division drive while avoiding signal interference by coordinating the ON periods of different buffer circuits.
Solution Approach 2:
The patent converts the harmful coupling capacitance between adjacent data lines into a beneficial effect by carefully controlling the timing of signal output from interleaved buffer circuits. The coupling capacitance is utilized to pre-charge or prepare adjacent data lines, reducing the overall power consumption while maintaining signal integrity.
3Object-affected harmful factors
If ON periods of time divisional switches are overlapped to reduce coupling capacitance effects, then display unevenness decreases, but electric power consumption increases
Solution Approach 1:
The patent segments data lines into two independently controlled groups, allowing precise timing control of signal output to each group. This segmentation enables the system to reduce display unevenness through coordinated timing without requiring prolonged overlapping ON periods that would increase power consumption.
Solution Approach 2:
The patent optimizes the timing parameters of buffer circuit operation to achieve the minimum necessary overlap period. By precisely controlling the duration and timing of signal output from each buffer circuit, the patent reduces display unevenness while minimizing the time during which multiple buffers are simultaneously active, thereby reducing power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces display unevenness, decreases the chip area of the driver IC, and maintains efficient power consumption by minimizing coupling capacitance between data lines, thereby improving the overall performance of the display apparatus.
Implementation Method 1
a coupling capacitance value between the wirings becomes large. Thus, in the driver IC in which the time divisional switches are provided to perform the time division drive on the amorphous TFT, the coupling capacitance value between the wirings influences a signal on the adjacent data line
Data Source
AI summary
A data line driving circuit includes a first buffer circuit configured to drive a data line, and a second buffer circuit configured to drive a data line. N first data lines (n is a natural number larger than 1), and m second data lines (m is a natural number larger than 1) are alternately arranged in units of data lines as a group. The data line driving circuit further includes a first switch circuit configured to select one of the n first data lines in a first ON period and to connect the selected first data line with the first buffer circuit, and a second switch circuit configured to select one of the m second data lines adjacent to the selected first data line in a second ON period and to connect the selected second data line with the second buffer circuit.