Global Data Line Shielding for Memory Noise Reduction

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Solution Overview

Problem

Memory devices face challenges in reducing noise couplings between propagation lines, which increases the global data path footprint and wastes space due to the presence of unused shield lines and simultaneous switching issues during high-speed operations.

Innovation Solution

The implementation of a staggered firing scheme and utilizing upper global data lines as shields for lower data lines, eliminating most DC shield lines, and tying data mask lines to a constant state to reduce coupling and maintain signal integrity, thereby minimizing the global data path footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DC shield lines are added between propagation lines to reduce noise coupling, then signal integrity is improved, but the global data path footprint increases

Engineering Contradiction:
Improvesignal integrityVSAvoidglobal data path footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes unnecessary DC shield lines from the global data path, extracting only the essential shielding functionality. By eliminating redundant shield lines while maintaining noise protection through alternative means (such as optimized line spacing and routing), the design reduces the footprint without completely removing shielding functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes existing data lines serve multiple functions - they act as both signal propagation lines and as shields for adjacent lines. This multi-functionality eliminates the need for dedicated DC shield lines, thereby reducing the overall footprint while maintaining signal integrity through cross-shielding effects.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Object-affected harmful factors

If shield lines are added to reduce coupling noise, then noise coupling is reduced, but device complexity increases

Engineering Contradiction:
Improvecoupling noiseVSAvoiddata path structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the functionality of signal transmission and noise shielding into a single integrated structure. By combining these functions, the design eliminates the need for separate DC shield lines, thereby reducing device complexity while still providing noise protection through the inherent capacitive coupling between adjacent data lines.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If simultaneous switching is used for high-speed operations, then operational speed is improved, but noise coupling between lines increases

Engineering Contradiction:
Improveoperational speedVSAvoidcoupling noise
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary design considerations in the physical layout and routing of data lines to prevent noise coupling before simultaneous switching occurs. By pre-positioning lines with optimal spacing and orientation, and pre-establishing capacitive coupling relationships, the design mitigates noise effects before high-speed switching operations begin, allowing faster operations with reduced coupling.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the size of the global data path by eliminating unnecessary shield lines and minimizing cross-talk between adjacent data lines, maintaining high signal integrity and reducing the overall footprint of memory devices.

Implementation Method 1

utilizing upper global data lines as shields for lower data lines

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Implementation Method 2

reducing noise couplings between propagation lines

Methodology Applied
Scientific EffectCapacitive coupling: Parasitic Capacitance

Data Source

PatentUS10403353B1Systems and methods for reducing coupling noise between propagation lines for die size efficiency
Publication Date: 2019.09.03 MICRON TECHNOLOGY INC
  • US10403353B1 patent drawing
  • US10403353B1 patent drawing
  • US10403353B1 patent drawing

AI summary

Devices, systems, and methods for reducing noise couplings between propagation lines for size efficiency. In one embodiment, a memory device is provided, comprising a memory array and an input/output (I/O) circuit. The I/O circuit can include a first plurality of global data lines and a second plurality of global data lines. The second plurality of global data lines are directly interleaved between the first plurality of global date lines and are configured to shield the first plurality of global data lines. In some embodiments, the first plurality of global data lines are shorter in length than the second plurality of global data lines and are switched before the second plurality of global data lines are switched.