Synchronous Data-Link Throughput via Phase and Duty Cycle Modulation
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Solution Overview
Problem
Current memory devices, such as DDR SDRAM, increase data throughput by raising the frequency of synchronization signals, which complicates and costs more to manufacture and modify processors, memory devices, and circuit boards.
Innovation Solution
Modulating the phase and duty cycle of a multi-bit signal using an internal clock not synchronized with an external synchronization signal, allowing for increased data transmission without frequency increases, thus maintaining complexity and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the synchronization signal is increased to increase data throughput, then the data transmission rate increases, but the manufacturing cost and device complexity increase
Solution Approach 1:
The patent changes the modulation parameters (phase and duty cycle) of the data signal instead of changing the frequency parameter of the synchronization signal. By modulating phase and duty cycle, multiple bits can be transmitted per synchronization cycle, achieving higher throughput without increasing frequency-related complexity
Solution Approach 2:
The patent transitions from single-dimension (frequency-based) throughput enhancement to multi-dimension modulation by utilizing both phase and duty cycle dimensions. This allows encoding multiple bits per synchronization cycle, effectively adding dimensional complexity to the signal modulation rather than simply increasing frequency
2Productivity
If the frequency of the synchronization signal is increased to increase data throughput, then the data transmission rate increases, but the manufacturing cost increases
Solution Approach 1:
The patent modifies signal parameters (phase and duty cycle) rather than hardware parameters (frequency). This software/firmware-level change avoids costly hardware redesign and manufacturing, reducing production costs while achieving the same throughput improvement
3Productivity
If more bits are transmitted during each cycle of the synchronization signal, then data throughput increases, but the complexity of the circuit board and bus increases
Solution Approach 1:
The patent uses the existing synchronization signal and data bus infrastructure to carry additional information through phase and duty cycle modulation. The existing circuit board and bus components serve multiple functions by decoding these modulated parameters, avoiding the need for additional dedicated hardware components
Data Source
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AI summary
A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.