Data Mapping for Non-Volatile Storage Bit Line Noise
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Solution Overview
Problem
The scaling down of memory device dimensions leads to significant parasitic capacitance between bit lines, causing coupling noise and read errors, which worsens sensing accuracy and increases bit line settling time, degrading read performance.
Innovation Solution
Implementing a data mapping method that senses odd-numbered bit lines separately from even-numbered bit lines, reducing coupling noise and bit line settling time, while maintaining backward compatibility through dual data buses and separate cache access lines for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device dimensions are scaled down, then storage density is improved, but parasitic capacitance between bit lines increases causing coupling noise and read errors
Solution Approach 1:
The patent segments the bit lines into two separate sets: odd-numbered bit lines and even-numbered bit lines. By sensing these sets separately through separate sense amplifiers and data buses, the patent reduces coupling noise between adjacent bit lines, thereby mitigating the harmful parasitic capacitance effect while maintaining high storage density enabled by dimension scaling.
2Measurement precision
If bit line settling time is increased to reduce coupling noise, then sensing accuracy is improved, but read performance is degraded
Solution Approach 1:
The patent divides the bit lines into odd and even sets that can be sensed in parallel through separate sense amplifiers. This segmentation allows both sets to be read simultaneously without interference, achieving fast read performance while maintaining high sensing accuracy by eliminating coupling noise between adjacent bit lines.
Solution Approach 2:
The patent introduces a dimensional separation by creating separate sense amplifier paths for odd and even bit lines. This additional dimension of separation in the sensing architecture allows independent simultaneous reading of both bit line sets, resolving the time-accuracy tradeoff.
3Measurement precision
If shield bit line sensing is implemented to reduce coupling noise, then sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by enabling the memory device to operate in multiple sensing modes: shield bit line sensing mode for high accuracy and conventional all bit line sensing mode for compatibility. The dual data buses and separate cache access lines can be configured to support both operating modes, making the complexity worthwhile by providing versatility.
Solution Approach 2:
The patent creates a dynamic, reconfigurable sensing architecture where the data mapping can be adapted between different sensing modes. The control circuitry can dynamically switch between shield bit line sensing and conventional sensing based on operational requirements, optimizing the balance between accuracy and complexity for different use cases.
4Productivity
If dual data buses and separate cache access lines are added for efficient data transfer, then read performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the data transfer infrastructure into separate components: dual data buses (first data bus for odd bit lines, second data bus for even bit lines) and separate cache access lines. This segmentation enables parallel data transfer paths that improve read performance by eliminating bottlenecks in the data retrieval process.
Solution Approach 2:
The patent adds dimensional separation to the data transfer architecture by introducing separate data buses and cache access lines for odd and even bit lines. This additional dimension of parallelism in the data transfer paths enables simultaneous data retrieval from both bit line sets, significantly improving read performance.
Data Source
AI summary
Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.