Tri-stating Data Mask Line for Bus Interrupt Signaling
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Solution Overview
Problem
Current memory systems lack an efficient method to utilize the data mask line during write operations, limiting additional communication channels between the memory controller and memory devices without increasing pin count.
Innovation Solution
The memory system employs a data mask line that is tri-stated during write operations, allowing it to function as a notification channel for status changes, error indications, or other events, enabling event-driven operations and reducing the need for polling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the data mask line is used only during write operations, then the write operation control function is maintained, but the communication efficiency is limited and additional pins are required for notification channels
Solution Approach 1:
The data mask line is designed to perform multiple functions: it serves as a control signal during write operations and as a notification channel during non-write operations. The memory device can assert the data mask line to notify the memory controller of status changes, error conditions, or other events without requiring additional pins. This multi-functional approach resolves the contradiction by enabling notification capability while maintaining the existing pin structure.
2Productivity
If the data mask line is continuously monitored for notifications, then event-driven operations are enabled, but write operations may be interfered with by noise or false signals
Solution Approach 1:
The data mask line's functionality dynamically changes based on the operation state. During write operations, the data mask line is held in a high-impedance state or explicitly controlled to prevent memory device assertions, ensuring write operation integrity. During non-write operations, the data mask line becomes active for notifications, enabling event-driven operations. This dynamic state management resolves the contradiction by ensuring reliability during writes while enabling responsiveness during idle periods.
Solution Approach 2:
The memory controller proactively manages the data mask line state before write operations occur. By pre-configuring the data mask line to be controlled during write operations and only allowing memory device assertions during non-write operations, the system prevents potential interference before it can occur. This preliminary configuration ensures that notification functionality is available when needed without compromising write operation integrity.
Data Source
AI summary
A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.