Data Masking Circuit Error Correction Parity Generation
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Solution Overview
Problem
As data transmission speeds increase in semiconductor devices, the likelihood of errors during data transmission also rises, necessitating additional measures to ensure data reliability, particularly in generating and correcting error codes for error detection and correction.
Innovation Solution
An electronic device is designed with a core circuit to store write data and parity, an error correction circuit to generate write parity from error-corrected read data, and a data processing circuit to correct errors and generate transfer data, supporting a write-back disable operation and enhancing data reliability through error correction and masking operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve productivity, then the operating speed of semiconductor device is improved, but the probability of error occurrence during data transmission increases, worsening reliability
Solution Approach 1:
The patent introduces error detection codes (EDC) and error correction codes (ECC) as intermediary elements that mediate between the data transmission process and the core circuit. These codes act as mediators that detect and correct errors without requiring retransmission, thus maintaining high data transmission speeds while improving reliability. The EDC and ECC circuits process the data alongside the core circuit, enabling error correction to occur in parallel with normal data operations.
Solution Approach 2:
The patent changes the parameter of data structure by adding error detection and correction code bits to the transmitted data. This parameter change allows the system to maintain high transmission speeds while incorporating reliability mechanisms. The error codes are generated and processed as additional parameters alongside the main data, enabling error correction without significantly impacting the core data transmission speed.
2Reliability
If error detection and correction codes are added to ensure data reliability, then data transmission reliability is improved, but the complexity of the device increases due to additional circuits
Solution Approach 1:
The patent merges the error detection and correction functions with the existing core circuit operations. The EDC and ECC circuits are integrated alongside the core circuit, sharing common data pathways and control mechanisms where possible. This merging approach allows error correction functionality to be added without creating completely separate, independent systems, thereby reducing the overall complexity increase compared to fully separate error correction systems.
3Reliability
If error correction operations are performed on all data to improve reliability, then data integrity is improved, but the processing time increases due to additional correction steps
Solution Approach 1:
The patent performs error detection code generation and error correction code generation in advance during the data writing process. The EDC is generated based on the data to be written, and the ECC is generated based on the EDC and data. This preliminary action allows error correction to be prepared beforehand, so that when data is read, the correction process is faster since the correction codes are already generated and ready to be applied immediately upon detecting errors.
Data Source
AI summary
An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.