Data Mover Circuitry for N-Dimensional Data Processing
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Solution Overview
Problem
Modern integrated circuits face challenges in processing large data sets that exceed the available on-chip memory, requiring efficient mechanisms to move and manage N-dimensional data both into and out of the IC.
Innovation Solution
The implementation of decomposer and composer data mover circuits that partition N-dimensional data into data tiles, including metadata headers for location information, allowing efficient processing and reassembly within the IC, and writing valid data regions back to external memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the entire data set is loaded into on-chip memory for processing, then processing speed and efficiency are improved, but the IC cannot handle data sets larger than available on-chip memory
Solution Approach 1:
The patent divides the large data set into smaller sub-arrays that can fit within on-chip memory. The decomposer circuitry partitions the N-dimensional data into multiple sub-arrays, each processed separately by the compute circuitry. This segmentation allows the IC to handle data sets larger than on-chip memory capacity while maintaining efficient processing speeds.
2Quantity of substance
If data is processed in portions using on-chip memory, then memory limitations are overcome, but processing efficiency decreases due to repeated data movement
Solution Approach 1:
The decomposer circuitry performs preliminary actions by pre-processing the data during the data movement phase. It calculates metadata headers, determines valid data regions, and organizes sub-arrays before they are loaded into on-chip memory. This preliminary organization reduces the need for repeated data movement and reorganization during processing, thereby maintaining higher processing efficiency.
Solution Approach 2:
The patent introduces data mover circuitry as an intermediary between external memory and compute circuitry. This intermediary handles the complex tasks of data partitioning, metadata generation, and coordinate transformation, allowing the compute circuitry to focus on efficient processing without being burdened by data management overhead.
3Productivity
If N-dimensional data is partitioned into sub-arrays with metadata headers, then data management efficiency is improved, but device complexity increases
Solution Approach 1:
The decomposer and composer circuitry are designed with multi-functionality to handle various N-dimensional data operations. The same circuitry that partitions data into sub-arrays also generates metadata headers, calculates coordinates, and manages data movement. This universal design reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity.
4Measurement precision
If metadata headers are generated for each sub-array, then location tracking precision is improved, but processing overhead increases
Solution Approach 1:
The metadata headers encode location information using coordinate transformations that change the parameter representation. By transforming coordinates from the original N-dimensional space to sub-array specific coordinates, the system achieves precise location tracking while using compact metadata structures that minimize processing overhead.
Data Source
AI summary
An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.