Data Output Circuit Dual-Edge Clock Synchronization
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high-speed data output operations while maintaining sufficient timing margins, as existing technologies struggle to synchronize control signals with data output effectively, leading to reduced valid data windows and limited high-speed data output capabilities.
Innovation Solution
A data output circuit with first and second data latch units and a data output unit that synchronizes preliminary output data with rising and falling clock edges, utilizing bank selection signals generated from clock information to ensure timely and efficient data transfer, thereby increasing the timing margin and data output rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are transferred in synchronization with both rising edge and falling edge of reference clock signal to increase data input/output rate, then productivity is improved, but timing margin between control signal and data output is reduced
Solution Approach 1:
The patent divides the data output operation into two separate segments: one synchronized with the rising edge of the clock signal and another with the falling edge. This segmentation allows each data group to be handled independently with appropriate timing, thereby maintaining sufficient timing margins while achieving high-speed dual-edge data transfer
Solution Approach 2:
The patent employs pipe registers to preliminarily store output data before the actual data output operation. This preliminary storage action allows the control signals to be generated and prepared in advance, ensuring adequate timing margins are maintained while enabling high-speed data transfer synchronized with both clock edges
2Productivity
If pipe register is employed to store plurality of output data for increasing data output rate, then productivity is improved, but timing margin between control signal and data output is reduced
Solution Approach 1:
The pipe register stores output data in advance before the data output operation is triggered. This preliminary storage ensures that when data transfer is initiated, the data are already prepared and available, allowing control signals to be generated with sufficient timing margins while maintaining high data output rates
Solution Approach 2:
The patent segments the data storage and output process by using pipe registers to hold data separately for rising edge and falling edge operations. This segmentation allows independent timing control for each data group, maintaining adequate timing margins while achieving high-speed dual-edge data output
Data Source
AI summary
A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.