Data Output Circuit for Semiconductor Memory with Phase-Separated Latches
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Solution Overview
Problem
Conventional semiconductor memory devices face inaccuracies in data writing and reading due to asymmetry of metal lines and process deviations, and the testing of complementary cells is not accurately performed, leading to insufficient current or voltage sensing and decreased sensing speed.
Innovation Solution
A data output circuit with multiple paths at the output side of a sense amplifier, including first and second latches that latch amplified differential data with the same and opposite phases, respectively, and a multiplexer that transfers differential data from global I/O lines to the sense amplifier, with control signals enabling/disabling the latches based on the type of memory cell, minimizing loading at the input side of the sense amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer is employed to couple complementary cell paths inversely with respect to true cell paths, then complementary cells can be tested without varying test patterns, but loading of the I/O lines is increased and sensing speed decreases
Solution Approach 1:
The patent divides the data output circuit into separate true cell paths and complementary cell paths that are independently configured. By segmenting the paths, the invention allows complementary cells to be tested using the inverse coupling mechanism while true cells use the normal path, thereby maintaining testing capability without universally increasing loading on all I/O lines.
Solution Approach 2:
The patent employs control signals to dynamically switch between true cell mode and complementary cell mode. The multiplexer is controlled to couple complementary cell paths inversely only when testing complementary cells, while true cell paths operate normally. This dynamic switching allows the system to adapt its configuration based on the cell type being accessed, preventing continuous loading increase.
2Adaptability or versatility
If multiple data paths are used for true and complementary cells, then complementary cells can be tested, but data from memory cells may not be sufficiently developed for sensing
Solution Approach 1:
The patent applies different configurations to different parts of the data output circuit based on the cell type. True cell paths maintain their original signal characteristics while complementary cell paths are specifically configured with inverse coupling. This local differentiation ensures that each path is optimized for its specific function, maintaining signal integrity and sensing accuracy for both cell types.
Solution Approach 2:
The patent introduces control signals as intermediaries that manage the coupling configuration between cell paths and I/O lines. These control signals enable the system to switch between normal and inverse coupling modes, ensuring that the appropriate path configuration is applied based on whether a true or complementary cell is being accessed, thereby maintaining data quality for sensing.
3Adaptability or versatility
If the true cell path and complementary cell path are located at the input side of the sense amplifier, then both cell types can be accessed, but loading of the I/O lines is increased
Solution Approach 1:
The patent segments the data output circuit into distinct true cell paths and complementary cell paths that operate independently. By segmenting the paths, the invention allows complementary cells to be tested using the inverse coupling mechanism while true cells use the normal path, thereby maintaining testing capability without universally increasing loading on all I/O lines.
Solution Approach 2:
The patent discards the conventional approach of using a single unified path configuration for both cell types. Instead, it recovers performance by implementing separate optimized paths where complementary cell paths use inverse coupling only when needed, thereby reducing unnecessary loading on I/O lines during normal true cell operations.
Data Source
AI summary
A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.