Data Output Circuit Clock Boosting for High-Speed Memory
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Solution Overview
Problem
In memory devices using the LPDDR method, high-speed data transmission is hindered by parasitic effects and increased equivalent resistance due to the multiplexing of data signals through multiple transistors, making accurate data output challenging.
Innovation Solution
A data output circuit is designed with a clock boosting circuit that generates boosted clock signals using a second power voltage, allowing data output drivers to synchronize and multiplex data signals at high speed, reducing equivalent resistance and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data signals are multiplexed through multiple transistors in the LPDDR method, then data transmission frequency can be increased to match clock frequency, but parasitic effects and equivalent resistance increase, making accurate high-speed data transception difficult
Solution Approach 1:
The data output circuit is divided into multiple independent output drivers (first output driver, second output driver, etc.), each handling separate data signals. Each output driver independently multiplexes its assigned data signals without sharing transistors with other drivers, thereby segmenting the parasitic effects and resistance sources that previously affected all multiplexed data collectively.
Solution Approach 2:
A dummy transistor is introduced as an intermediary element connected between the data signal line and ground. This dummy transistor acts as a mediator that compensates for the parasitic effects and equivalent resistance introduced by the multiplexing transistors, thereby maintaining signal integrity and enabling accurate high-speed data transception despite the presence of multiple multiplexing transistors.
2Productivity
If multiple transistors are used for multiplexing data signals, then data can be multiplexed and output via output pads, but the equivalent resistance of the plurality of transistors increases, hindering high-speed accurate data output
Solution Approach 1:
The data output function is segmented across multiple independent output drivers, each responsible for specific data signals. This segmentation allows each driver to optimize its transistor configuration for minimal resistance while maintaining the overall multiplexing capability of the system, thereby preserving signal integrity during high-speed data output.
Solution Approach 2:
The dummy transistor serves as an intermediary that compensates for the cumulative equivalent resistance of the multiplexing transistors. By providing an additional conduction path to ground, it balances the resistance effects and maintains proper signal levels, ensuring data signal integrity is preserved despite the presence of multiple multiplexing transistors in each output driver.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate high-speed data transmission while reducing the design area of the memory device by minimizing transistor size and resistance, enhancing data output efficiency.
Implementation Method 1
a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage
Data Source
AI summary
A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.