Data Output Clock Generating Circuit for Semiconductor Memory
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Solution Overview
Problem
In high-speed semiconductor memory apparatuses, the timing margin between output enable signals and clocks is reduced, leading to improper data output clocks and potential erroneous data output operations due to decreased timing margins.
Innovation Solution
A data output clock generating circuit that independently drives rising and falling data output clock generating units, using clock extraction signals to ensure predetermined timing margins by combining output enable signals with clocks from a DLL circuit, and utilizing flip-flops to control enable and disable times for generating stable data output clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to achieve high-speed data input/output operation, then productivity is improved, but timing margin between output enable signals and clocks is reduced leading to reliability deterioration
Solution Approach 1:
The clock signal is segmented into separate rising clock and falling clock signals, each processed independently through dedicated clock extraction circuits. This segmentation allows precise control of timing margins for each clock edge separately, preventing the timing conflicts that would occur with a unified clock processing approach at high frequencies
Solution Approach 2:
A clock extraction circuit is introduced as an intermediary component between the DLL circuit and the data output buffers. This intermediary extracts and conditions the clock signals, generating clean rising and falling clock signals with proper timing margins independent of the high-frequency DLL clock, thereby mediating between the high-speed clock source and the timing-sensitive output stage
2Productivity
If DLL clock frequency is increased to achieve DDR speed, then productivity is improved, but timing margin for data output operation is reduced causing erroneous operations
Solution Approach 1:
The data output operation is segmented into separate rising edge output and falling edge output paths, each with its own clock extraction and timing control. This allows independent optimization of timing margins for each data output phase, ensuring reliable operation even when the overall DLL clock frequency is high
Solution Approach 2:
The clock extraction circuit performs preliminary action by pre-processing the DLL clock signals to generate properly timed rising and falling clock signals before they reach the data output buffers. This preliminary timing adjustment ensures that adequate timing margins are established in advance, preventing erroneous operations during high-speed data output
Data Source
AI summary
A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.