Data Output Control Circuit With DLL Phase Correction
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Solution Overview
Problem
Semiconductor integrated circuits face limitations in operable frequency range, accuracy of phase synchronization, and layout area due to constraints in delay clock setup and hold times, PVT variations, and the need for multiple delay chains and flip-flops with increasing CAS latency.
Innovation Solution
A data output control signal generating circuit that includes a delay correction signal generator and a column address strobe latency control multiplexer, which detects and compensates for phase differences between clocks and delay locked loop clocks, allowing for flexible output enable signal selection and minimizing the number of delay chains and flip-flops required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay chains and flip-flops are used to compensate for delay times in data output control signal generation, then phase synchronization accuracy is improved, but device complexity and layout area increase
Solution Approach 1:
The patent combines multiple delay chains into a single delay chain by using a binary-weighted structure where each tap corresponds to a power of two delay unit. This merging approach achieves the same phase compensation capability with fewer components, directly reducing device complexity while maintaining measurement precision.
Solution Approach 2:
The single delay chain is designed to serve multiple CAS latency values simultaneously through binary-weighted taps. Each tap can be selectively activated to provide the required phase compensation for different latency requirements, making the structure universal and eliminating the need for separate delay chains for each CAS latency value.
2Measurement precision
If multiple delay chains and flip-flops are used to compensate for delay times, then phase synchronization accuracy is improved, but layout area increases
Solution Approach 1:
The patent merges multiple delay chains into a single compact structure using binary-weighted delay units. This consolidation dramatically reduces the layout area while maintaining the ability to achieve precise phase synchronization through selective tap activation.
Solution Approach 2:
The delay chain is segmented into binary-weighted units (1x, 2x, 4x, 8x, etc.) that can be independently selected. This segmentation allows the circuit to achieve any required delay value through combinatorial selection of taps, reducing the need for extensive physical delay chain implementations.
3Reliability
If delay clock setup and hold times are constrained, then reliability is improved, but operable frequency range is limited
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay amount can be programmatically controlled through tap selection. This dynamic capability allows the circuit to adaptively compensate for varying delay requirements at different operating frequencies, maintaining setup and hold time compliance across a wider frequency range.
Solution Approach 2:
The circuit changes the delay parameter dynamically by selecting different tap combinations based on operating conditions. This parameter adjustment capability enables the system to maintain reliable operation (meeting setup and hold times) while operating across an expanded frequency range that would otherwise be constrained by fixed delay requirements.
Data Source
AI summary
The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal.