Data Packet Processing Method for SoC Systems

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Solution Overview

Problem

The high CPU usage and resource occupation caused by processing large volumes of data packets in System on Chip (SoC) systems, leading to reduced hardware efficiency and delayed information processing, especially in applications requiring timely responses, due to conventional interrupt mechanisms.

Innovation Solution

A data packet processing method that differentiates between high priority and normal data packets based on key messages, executing immediate interrupts for high priority packets and interrupt moderation for normal packets, allowing for instantaneous processing of high priority data and efficient handling of normal data packets by delaying processing until a predetermined amount or time-out is reached.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interrupt moderation method is applied to reduce CPU usage rate, then hardware efficiency is enhanced, but data packet transmission is postponed and information processing is delayed

Engineering Contradiction:
Improvehardware efficiencyVSAvoiddata packet transmission delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies different interrupt handling strategies to different data packets based on their priority levels. High priority packets trigger immediate interrupts for instant processing, while normal priority packets use interrupt moderation. This local differentiation resolves the contradiction by ensuring time-sensitive packets are processed without delay while maintaining hardware efficiency for other packets.

Inventive Principle:
Principle #3Local quality

2Reliability

If each data packet is sent to CPU for individual processing, then data processing is timely, but CPU usage rate becomes too high and system resource occupation increases

Engineering Contradiction:
Improvedata processing timelinessVSAvoidhardware efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent differentiates between high priority and normal priority data packets, applying individual processing only to high priority packets while using interrupt moderation for normal packets. This selective approach ensures timely processing for critical data while improving overall hardware efficiency by reducing unnecessary individual processing.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments data packets into different priority levels (high priority and normal priority) and applies different processing mechanisms to each segment. This segmentation allows the system to balance between timely processing and hardware efficiency by treating different packet types differently.

Inventive Principle:
Principle #1Segmentation

3Productivity

If interrupt moderation waits for more packets or time-out before generating interrupt, then CPU usage rate is reduced, but response timeliness for applications requiring immediate processing is compromised

Engineering Contradiction:
ImproveCPU usage rateVSAvoidresponse timeliness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies interrupt moderation selectively only to normal priority packets while using immediate interrupts for high priority packets. This local application of interrupt moderation reduces CPU usage for non-critical packets without compromising response timeliness for applications requiring immediate processing.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10528500B2Data packet processing method
Publication Date: 2020.01.07 REALTEK SEMICON CORP
  • US10528500B2 patent drawing
  • US10528500B2 patent drawing
  • US10528500B2 patent drawing

AI summary

A data packet processing method comprises: receiving data packet including a key message; analyzing the key message; determining whether the data packet is a high priority data packet or a normal data packet according to a result of analyzing the first key message of the data packet; and executing an Rx high priority interrupt in response to determining that the data packet is the high priority data packet. The Rx high priority interrupt is to immediately transmit an interrupt signal to interrupt receiving of the data packets.