Hierarchical Synthesis Tool for Data Path Cluster Optimization
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Solution Overview
Problem
The existing data path architectures selected during register-transfer level (RTL) synthesis are often suboptimal due to inaccurate predictions of area usage, timing delays, and power consumption, as physical effects are difficult to predict before placement and routing, and typical logic synthesis tools do not revisit or refine the data path architecture post-implementation.
Innovation Solution
A framework for optimizing and refining data path operators during physically-aware logic synthesis, using a hierarchical synthesis tool with super-builders that explore multiple architectures, store original builder information, and rebuild data path clusters to minimize area while meeting user-specified timing constraints, and enable parallel architecture exploration through super-threading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data path architecture is selected during RTL synthesis without considering physical effects, then design process is simple and fast, but area usage, timing delays, and power consumption predictions are inaccurate
Solution Approach 1:
The patent performs preliminary physical effects analysis and data path architecture evaluation during RTL synthesis by integrating with place and route tools. This allows the system to predict actual physical effects (area, timing, power) before final implementation, enabling informed architecture selection without sacrificing design process speed through automated co-simulation and prediction algorithms.
Solution Approach 2:
The patent implements a feedback mechanism where place and route tool outputs (actual physical measurements) are fed back to the logic synthesis tool. This feedback loop allows continuous refinement of data path architecture predictions based on actual physical effects, improving prediction accuracy while maintaining design efficiency through iterative optimization.
2Productivity
If data path architecture is selected without post-implementation review, then design process is efficient, but suboptimal architectures cannot be improved
Solution Approach 1:
The patent enables post-implementation review by establishing a feedback loop where place and route results are analyzed and fed back to the logic synthesis tool. This allows the system to identify suboptimal architectures after implementation and automatically generate improved alternatives, ensuring design optimality without significantly impacting overall design efficiency through targeted re-synthesis.
Solution Approach 2:
The patent makes the data path architecture selection process dynamic by allowing multiple passes of synthesis and evaluation. The system can revisit and refine architecture decisions at different stages of the design flow based on emerging physical information, transitioning from static single-pass synthesis to adaptive multi-pass optimization.
3Measurement precision
If physical effects are considered in data path selection, then prediction accuracy improves, but design complexity increases
Solution Approach 1:
The patent introduces an intermediary layer that bridges logic synthesis and place and route tools. This intermediary component handles the complex physical effects analysis and architecture evaluation, translating physical measurements into synthesis-friendly feedback without requiring the synthesis tool itself to become overly complex. The intermediary manages the integration complexity while preserving tool simplicity.
4Device complexity
If data path architecture is fixed after RTL synthesis, then design flow is simple, but opportunities for optimization are lost
Solution Approach 1:
The patent transforms the fixed data path architecture approach into a dynamic, multi-stage optimization process. The system allows architecture re-evaluation and re-synthesis at multiple points in the design flow based on physical feedback, enabling continuous improvement of design quality without permanently increasing design flow complexity through selective re-optimization.
Data Source
AI summary
In one embodiment of the invention, a method of logic synthesis is disclosed. The method includes generating a plurality of design architecture alternatives for circuit logic of a data path cluster; saving the plurality of design architecture alternatives; and evaluating the plurality of design architecture alternatives in response to design constraints to select a preferred design architecture.