Data Path Interface Circuit Synchronization Delay Control
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Solution Overview
Problem
Current semiconductor memory systems face issues with inconsistent data transmission speeds across different memory blocks, leading to unsynchronized data transmission and timing inconsistencies during writing and reading operations.
Innovation Solution
A data path interface circuit is introduced, comprising a writing path module, a reading path module, a delay module, and a delay control module, which performs delay processing on data to ensure synchronized transmission by adjusting the delay time based on signal instructions, thereby synchronizing data transmission across memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory blocks are arranged to achieve greater memory space, then storage capacity is improved, but data transmission synchronization deteriorates due to different transmission speeds across memory blocks
Solution Approach 1:
The delay control module pre-calculates and pre-configures the required delay amounts for each memory block based on their respective data transmission speeds. This preliminary action ensures that data from different memory blocks will arrive at the same time without requiring real-time adjustments during data transmission operations.
Solution Approach 2:
The patent introduces adjustable delay parameters for different memory blocks through the delay control module. By dynamically changing the delay time parameter for each memory block according to its transmission speed characteristics, the system achieves synchronized data arrival at the same time, resolving the synchronization issue while maintaining expanded memory capacity.
2Quantity of substance
If data transmission paths are extended to connect multiple memory blocks, then memory capacity is increased, but transmission timing consistency deteriorates
Solution Approach 1:
The delay control module applies localized delay adjustments to each memory block based on its specific transmission characteristics. Instead of using a uniform delay for all blocks, the system tailors the delay parameter individually for each memory block, compensating for differences in transmission path lengths and speeds to achieve overall timing consistency.
Data Source
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AI summary
The embodiments of the present application relate to a data path interface circuit, a memory and a memory system. The data path interface circuit includes: a writing path module, connected to an internal port and an external port respectively and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and the external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and the internal port respectively and configured to obtain the stored data from the external port or the internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or the reading path module; and a delay control module connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.