Data-Path Protection Using LBA-Embedded CRC and ECC

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Solution Overview

Problem

Current data storage systems in disk drives face challenges in reliably detecting and correcting errors during read and write operations, particularly due to limitations in cyclic redundancy check (CRC) and error-correcting codes, which may not detect errors when data differs between write and read operations, and cannot correct all types of errors.

Innovation Solution

A system comprising a host FIFO module, first and second encoder modules, and a control module that generates and compares checksums to ensure data integrity by embedding logical block addresses (LBAs) within checksums, enabling detection and correction of errors through a combination of CRC and ECC encoding, and using linear feedback shift registers (LFSRs) for efficient error checking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CRC and ECC encoding are used for error detection and correction, then data reliability is improved, but device complexity increases due to multiple encoder modules and checksum comparison mechanisms

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines CRC encoding and ECC encoding into a unified error protection system. The first encoder module generates CRC checksums while the second encoder module generates ECC checksums, and both are integrated into the same data path with a single control module that coordinates their operation. This merging approach improves data reliability through multiple error detection and correction mechanisms while managing device complexity by using a unified control structure rather than separate independent systems.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If multiple encoder modules generate and compare checksums for error detection, then measurement precision of data integrity is improved, but loss of time occurs during checksum generation and comparison operations

Engineering Contradiction:
Improvedata integrity detection accuracyVSAvoidtime for checksum generation and comparison
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs error detection and correction operations in advance during the write path. The first encoder module generates CRC checksums and the second encoder module generates ECC checksums before data is written to the disk. By performing these encoding operations preliminarily, the system ensures high measurement precision for data integrity without adding time delays during critical read operations, as the checksums are already prepared and stored with the data.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If LBA information is protected alongside data using CRC, then reliability of address identification is improved, but device complexity increases due to embedding LBA within checksums

Engineering Contradiction:
ImproveLBA identification reliabilityVSAvoidchecksum embedding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges LBA protection with data protection by using the same CRC and ECC encoding mechanisms for both. The control module appends LBA information to the data block, and the encoder modules generate checksums that cover both the data and the LBA information together. This unified approach improves LBA identification reliability while managing complexity by using the existing encoding infrastructure rather than creating separate protection mechanisms for addresses.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9129654B1Systems and methods for data-path protection
Publication Date: 2015.09.08 MARVELL ASIA PTE LTD
  • US9129654B1 patent drawing
  • US9129654B1 patent drawing
  • US9129654B1 patent drawing

AI summary

A system including a first first-in first-out (FIFO) module, a control module, and a second FIFO module. The first FIFO module is configured to receive, from a host, (i) a first block and (ii) a first logical block address corresponding to the first block, where the first block includes first data. The control module is configured to generate a second block, where the second block includes (i) the first data and (ii) the first logical block address. The second FIFO module is configured to receive a third block from the first FIFO module, where the third block includes a second logical block address, and to determine whether the third block is different than the first block depending on whether the second logical block address included in the third block is different than the first logical block address included in the second block.