Data Plane Message Recording Using External Memory Buffers
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Solution Overview
Problem
There is a need for enhanced data plane circuit architectures to augment functionality and manage data message forwarding efficiently, as existing circuits face challenges in processing and scheduling data messages effectively across networks.
Innovation Solution
The integration of field programmable gate arrays (FPGAs) and external memories within the data plane circuit to implement deep buffers and scheduling mechanisms, allowing for efficient data message processing and forwarding by determining the optimal time for message retrieval and forwarding through the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data messages are stored in external memory for deep buffering, then the data plane circuit can handle higher traffic volumes and improve productivity, but the device complexity increases due to additional FPGAs and memory circuits
Solution Approach 1:
The patent divides the data plane circuit into multiple message processing pipelines, each capable of independent operation. External memories are segmented into multiple banks that can be accessed simultaneously by different pipelines, enabling parallel processing and increasing overall productivity without proportionally increasing complexity.
Solution Approach 2:
The patent implements a hierarchical architecture where FPGAs are integrated within the data plane circuit and external memories are coupled to the FPGAs, creating a nested structure. This allows the system to manage complexity by organizing components in layers, with each layer handling specific functions.
2Reliability
If FPGAs implement scheduling operations for data messages, then the reliability of data message forwarding is improved, but the device complexity increases due to additional programmable logic circuits
Solution Approach 1:
The FPGAs are designed to perform multiple functions: they interface between the data plane circuit and external memories, implement scheduling operations for data message retrieval, and can be reconfigured for different scheduling algorithms. This multi-functionality improves reliability without requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent utilizes the reconfigurable nature of FPGAs to dynamically adapt scheduling operations based on traffic conditions and requirements. This dynamic capability enhances forwarding reliability by allowing the system to respond to changing network conditions while using a single adaptable hardware platform.
3Loss of time
If external memories are used to store data messages temporarily, then the loss of time for message buffering is reduced, but the volume of external memory required increases
Solution Approach 1:
The patent implements continuous data message flow between the data plane circuit and external memories through multiple parallel pipelines and memory banks. By keeping the data flow continuous and avoiding idle periods, the system reduces the effective buffering time required while managing memory volume efficiently through sustained data movement.
Solution Approach 2:
The patent transitions from a single-dimensional memory access model to a multi-dimensional architecture with multiple memory banks that can be accessed in parallel by different pipelines. This dimensional expansion allows the system to reduce buffering time by simultaneously servicing multiple data streams, effectively trading memory organization for time efficiency.
Data Source
AI summary
Some embodiments provide novel circuits for recording data messages received by a data plane circuit of a forwarding element in an external memory outside of the data plane circuit. The external memory in some embodiments is outside of the forwarding element. In some embodiments, the data plane circuit encapsulates the received data messages that should be recorded with encapsulation headers, inserts into these headers addresses that identify locations for storing these data messages in a memory external to the data plane circuit, and forwards these encapsulated data messages so that these messages can be stored in the external memory by another circuit. Instead of encapsulating received data messages for storage, the data plane circuit in some embodiments encapsulates copies of the received data messages for storage. Accordingly, in these embodiments, the data plane circuit makes copies of the data messages that it needs to record.