Data Processing Array Direction Selection for Matrix Multiplication
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently performing matrix multiplication operations, particularly in generic application frameworks where matrices are stored in the same memory layout, requiring elements from one matrix to be accessed contiguously while others are discontiguous, leading to inefficiencies in delivering inputs for CPU instructions.
Innovation Solution
The proposed solution enables data processing apparatus and methods that allow accessing n x n storage locations as linear arrays in two different directions, enabling 'on-the-fly transpose capability, allowing for efficient delivery of input matrix elements regardless of memory layouts, by using instruction decoder circuitry to control instruction processing circuitry to access storage locations in selected array directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If matrices are stored in the same memory layout with contiguous access for one matrix and discontiguous access for another, then memory storage is simplified, but processing efficiency deteriorates due to inefficient input delivery for CPU instructions
Solution Approach 1:
The patent implements dynamic array direction selection where the processing circuitry can switch between first array direction (row-major) and second array direction (column-major) based on the specific operation requirements. This allows the system to adaptively optimize memory access patterns for different matrix operations without being constrained to a single fixed layout, thereby improving processing efficiency while maintaining implementation simplicity
Solution Approach 2:
The patent introduces a dual-directional access mechanism that treats the n x n storage locations as accessible in two different dimensions: row-major order (first array direction) and column-major order (second array direction). This dimensional flexibility allows efficient access to both contiguous and discontiguous elements without requiring separate physical storage layouts, resolving the contradiction between processing efficiency and memory layout complexity
2Adaptability or versatility
If array access is restricted to a single direction, then implementation simplicity is maintained, but versatility in handling different matrix operations deteriorates
Solution Approach 1:
The patent designs the processing circuitry with multi-functional array access capability, where the same hardware structure can access storage locations in either row-major or column-major direction based on instruction parameters. This universal access mechanism enables the system to handle various matrix operations (row operations, column operations, transpositions) without requiring separate dedicated circuits, thereby improving versatility while maintaining implementation simplicity
Solution Approach 2:
The patent utilizes instruction parameters to dynamically change the array access direction parameter. The array access instruction includes parameters that specify whether to access in the first array direction or second array direction, allowing the same hardware to adapt its behavior based on operational requirements. This parameter-driven flexibility improves adaptability while avoiding the need for complex hardwired control logic
Data Source
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AI summary
Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n x n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.