Data Processing Circuit for DDR Sampling Point Control
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Solution Overview
Problem
In semiconductor memory devices supporting dual data rate (DDR) operations, deviations in the duty cycle of clock signals reduce the margin of the data valid window, affecting system stability, and existing solutions require additional compensation circuits for process, voltage, and temperature variations.
Innovation Solution
A data processing circuit with a delay circuit generating delayed data signals and an output control circuit that samples these signals at different edges of a sampling clock signal, allowing independent control of the sampling point without altering the duty cycle, thereby maximizing the data valid window without the need for a duty control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the duty cycle of the clock signal is adjusted to maximize the data valid window, then the margin of the data valid window is improved, but the system requires additional compensation circuits for PVT variations
Solution Approach 1:
The invention divides the duty cycle adjustment into two independent segments: one for the rising edge and one for the falling edge. Each edge has its own delay circuit and selection mechanism, allowing independent optimization without requiring complex inter-edge compensation circuits. This segmentation resolves the contradiction by achieving reliable duty cycle control while minimizing device complexity.
Solution Approach 2:
The invention performs preliminary adjustment of the data signal timing through delay circuits before the sampling edge occurs. By pre-adjusting the data signals to align with the sampling clock edges, the system maximizes the data valid window margin without needing complex real-time compensation circuits for PVT variations.
2Reliability
If a duty adjusting circuit is used to directly change the duty cycle, then the margin of the data valid window is improved, but the device complexity increases due to additional compensation circuits
Solution Approach 1:
The duty adjusting function is segmented into independent rising-edge and falling-edge adjustment paths. Each path has its own delay circuit and selection logic, eliminating the need for a complex unified duty adjusting circuit with PVT compensation. This segmentation achieves reliable duty cycle control while reducing overall device complexity.
Solution Approach 2:
The invention applies different delay adjustments locally to each edge independently based on its specific timing requirements. Rather than using a global duty adjusting circuit that must compensate for all variations, each edge receives tailored local adjustment, improving reliability while minimizing the need for complex compensation mechanisms.
3Reliability
If the sampling point is controlled independently for each edge, then the data valid window margin is improved, but the device complexity increases
Solution Approach 1:
The sampling point control is segmented into independent rising-edge and falling-edge control paths. Each path has dedicated delay circuits and output control logic that operate independently, allowing optimal sampling point adjustment for each edge without requiring complex inter-dependent control mechanisms. This achieves improved data valid window margin while keeping device complexity manageable through modular design.
Data Source
AI summary
A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.