Data Processing Device With Delay Circuits For Power Supply Noise Reduction
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Solution Overview
Problem
High power consumption in semiconductor devices leads to rapid changes in power consumption, causing voltage drops or rises and increased power supply noise, which can result in malfunction and reduced reliability, especially in systems with multiple semiconductor devices.
Innovation Solution
A data processing device is designed with an instruction issue circuit and multiple execution circuits, where delay circuits are introduced to stagger the arrival timings of instructions to the execution circuits, allowing for different delay amounts to be set, which helps in canceling out power supply noise by aligning the phases of power supply noise waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple execution circuits operate simultaneously to improve processing throughput, then productivity increases, but power supply noise increases due to rapid power consumption changes
Solution Approach 1:
The patent applies periodic action by introducing delay circuits that create periodic timing offsets in instruction arrival at execution circuits. The delay amounts are set to integer multiples of half the power supply noise period, causing execution circuits to operate in a periodic staggered manner rather than simultaneously, thereby reducing power supply noise while maintaining overall productivity
Solution Approach 2:
The patent implements dynamics by making the delay amounts adjustable and configurable for different execution circuits. The delay circuits can dynamically control the timing of instruction arrival based on the specific power supply noise characteristics and operational requirements, allowing the system to adaptively balance throughput and noise reduction
2Speed
If instructions are issued to multiple execution circuits at the same time to maximize parallel processing, then processing speed increases, but voltage drops or rises occur due to rapid power consumption changes
Solution Approach 1:
The delay circuits introduce periodic timing offsets in instruction delivery to execution circuits. By setting delay amounts to integer multiples of half the power supply noise period, the system creates a periodic staggered execution pattern that distributes power consumption changes over time, preventing instantaneous voltage drops or rises while maintaining high processing speed
Solution Approach 2:
The delay circuits perform preliminary action by advancing the timing control of instruction delivery. Instructions are delayed before reaching execution circuits, allowing power consumption changes to be spread out in time. This preliminary timing adjustment prevents simultaneous power consumption spikes that would cause voltage instability
3Object-generated harmful factors
If delay circuits are introduced to stagger instruction arrival timings, then power supply noise is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the instruction delivery path into separate segments with individual delay circuits for different execution circuits. Each delay circuit is an independent module that can be configured with specific delay amounts, allowing the system to reduce power supply noise through distributed timing control while maintaining modular architecture
Solution Approach 2:
The delay circuits serve as intermediary components between the instruction issue circuit and execution circuits. These intermediary elements introduce controlled delays in instruction delivery, acting as buffers that stagger the arrival timings and reduce power supply noise without directly modifying the execution circuits or instruction issue circuit
Data Source
AI summary
A data processing device includes an instruction issue circuit configured to issue instructions; a plurality of execution circuits configured to execute, in parallel, the instructions issued from the instruction issue circuit; and a plurality of delay circuits configured to delay arrival timings of when the instructions issued from the instruction issue circuit arrive at the plurality of execution circuits, the plurality of delay circuits being arranged between the instruction issue circuit and the plurality of execution circuits. The arrival timings of the instructions arriving at at least two execution circuits included in the plurality of execution circuits are different from each other.