Data Processing Unit Address Generation With Split Register Offsets
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Solution Overview
Problem
Existing data processing units face inefficiencies in memory address generation due to the need for large numbers of registers and circuit complexity, limiting flexible memory addressing capabilities.
Innovation Solution
A data-processing unit with a register unit and an address-generation unit that fetches base and offset addresses with fewer bits than the memory address, allowing for the generation of memory addresses through addition and optional bit reordering or modulo operations, reducing the need for special-purpose registers and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of dedicated registers are used for address generation, then flexible memory addressing capability is improved, but circuit area increases
Solution Approach 1:
The patent uses general-purpose registers that can serve both as data registers and as address registers. The same register file is utilized for multiple purposes: storing data operands and storing address components (base address, offset address, step value). This eliminates the need for separate dedicated address registers, thereby reducing circuit area while maintaining flexible memory addressing capability through software-configurable register assignments.
2Adaptability or versatility
If special-purpose registers are used for address generation, then addressing mode versatility is improved, but device complexity increases
Solution Approach 1:
The patent employs a unified register file that serves multiple functions including storing base addresses, offset addresses, step values, and data operands. The address generation unit flexibly configures which general-purpose registers to use for address components based on addressing mode instructions, eliminating the need for specialized dedicated registers for each addressing mode and thereby reducing device complexity.
Solution Approach 2:
The patent implements dynamic register assignment where the role of registers (whether they store base address, offset, step value, or data) is determined at runtime based on the instruction being executed. This dynamic configuration allows the same hardware resources to adapt to different addressing modes without requiring static dedicated structures for each mode, reducing overall device complexity.
3Adaptability or versatility
If more registers are allocated for address components, then addressing flexibility is improved, but manufacturing cost increases
Solution Approach 1:
The patent reduces manufacturing cost by eliminating redundant dedicated address registers and using existing general-purpose registers for address storage. The same register file infrastructure serves both data and address purposes, reducing the total number of registers that need to be manufactured and reducing overall circuit area, thereby lowering manufacturing costs while maintaining addressing flexibility through software control.
Data Source
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Figure 2
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AI summary
A data-processing unit comprises a register unit (10) comprising a register (20, R0-R3). The data-processing unit further comprises an address-generation unit (30) for generating a memory address to a memory unit (60). The address-generation unit (30) is adapted to fetch, from the register (20, R0-R3), a base address stored in a first portion (20a) of the register (20, R0-R3) and a first offset address stored in a second portion (20b) of the register (20, R0-R3). The base address and the first offset address are represented with fewer bits than the memory address. The address generation unit (30) is adapted to receive a first instruction and, in response thereto, generate a second offset address based on the first offset address, and generate the memory address by adding the base address and the second offset address. A method for generating the memory address is also disclosed.