Data Processing Device Voltage Range Operation Mode
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Solution Overview
Problem
Existing data processing devices face challenges in efficiently setting operation voltage and clock frequency, leading to increased program steps and power consumption, particularly when transitioning between different operational modes such as voice and data communication, and require complex monitoring circuits for Dynamic Voltage and Frequency Scaling (DVFS) control.
Innovation Solution
A data processing device with a central processing unit that operates in multiple modes (high-speed, wide voltage range, and low power consumption) allowing user-settable operation modes, featuring a first clock circuit for the CPU and non-volatile memory, enabling flexible voltage and frequency settings to optimize power usage based on the device's state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS control technology is used to modify clock and power supply voltage according to operation state, then power consumption is reduced, but circuit scale and power consumption of monitoring circuit increase
Solution Approach 1:
The patent extracts the monitoring function from a separate complex monitoring circuit and integrates it into the CPU's existing program execution mechanism. The CPU monitors its own operation state through program counters and instruction flags, eliminating the need for external monitoring circuits while maintaining DVFS control capabilities.
Solution Approach 2:
The CPU is designed to serve multiple functions: it executes user programs for data processing while simultaneously acting as a monitoring circuit for DVFS control. The same CPU resources (program counter, instruction decoder, flags) are used for both computation and state monitoring, reducing overall circuit complexity.
2Use of energy by moving object
If DVFS control technology is used to modify clock and power supply voltage according to operation state, then power consumption is reduced, but the amount of consumed electric power becomes difficult to estimate during design
Solution Approach 1:
The patent uses parameter changes in the form of operation modes (first mode with higher voltage/frequency, second mode with lower voltage/frequency) that are predetermined and selectable. These discrete parameter sets make power consumption estimation easier during design compared to continuous DVFS adjustments, while still enabling significant power savings through mode switching.
Solution Approach 2:
The system dynamically switches between predetermined operation modes based on actual power availability and processing requirements. This dynamic mode switching provides flexibility in power management while maintaining predictable power consumption characteristics associated with each mode, facilitating design-time estimation.
3Adaptability or versatility
If program execution is used to control clock and power supply voltage settings, then flexibility is improved, but the number of program steps increases and code efficiency deteriorates
Solution Approach 1:
The patent segments the operation control into distinct, predefined modes (first operation mode, second operation mode) with specific voltage and frequency characteristics. This segmentation allows the system to achieve flexibility through mode selection rather than complex programmatic control of individual parameters, improving code efficiency while maintaining adaptability.
Solution Approach 2:
The operation modes are preliminarily configured with specific voltage and frequency settings optimized for different scenarios. This preliminary action eliminates the need for runtime calculation and adjustment of parameters, reducing program steps while maintaining the flexibility to adapt to different operational requirements through simple mode switching.
Data Source
AI summary
A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.