Integrated Data Processor with Dynamic Bus Arbitration
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Solution Overview
Problem
Existing data processing systems for image recognition and display control in applications like in-vehicle navigation systems face challenges in achieving real-time performance and high data bandwidth, leading to issues such as distorted displays, data loss, and reduced image recognition precision due to the need for large storage capacity and conflicting memory access demands.
Innovation Solution
A data processor is formed on a single semiconductor chip, incorporating a central processing unit, graphic controller, display controller, image recognizing module, and memory controller, with bus arbitration circuits to manage real-time performance and high data bandwidth requirements, and format conversion capabilities to handle various image data formats like YUV and RGB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large-capacity memory is mounted to satisfy real-time performance and high data bandwidth requirements, then real-time image recognition and display control can be assured, but system cost increases and device complexity increases
Solution Approach 1:
The patent combines the image recognizing module with real-time modules (display controller and image data input unit) on the same semiconductor chip, forming an integrated system that shares a common external memory. This merging eliminates the need for separate large-capacity memory for the image recognizing module, reducing system complexity and cost while maintaining real-time performance through coordinated bus arbitration.
2Reliability
If the image recognizing module is given highest priority in bus arbitration to assure real-time performance, then image recognition can be performed every display frame, but data bandwidth for non-real-time modules (CPU and graphic module) becomes insufficient
Solution Approach 1:
The patent implements dynamic bus arbitration where the image recognizing module's priority is adjusted based on its operational state. When the module requires both real-time performance and high data bandwidth (such as during active image processing), it is granted highest priority. This dynamic adjustment ensures that non-real-time modules receive sufficient bandwidth during periods when real-time constraints are less critical, balancing both requirements without needing separate memory systems.
3Device complexity
If multiple modules share a common external memory to reduce system cost, then device complexity decreases, but conflicts in memory access occur that degrade real-time performance and data bandwidth
Solution Approach 1:
The patent segments the bus arbitration into multiple levels: a first arbitration circuit handles real-time modules (display controller, image data input unit), while a second arbitration circuit handles non-real-time modules (CPU, graphic module). This segmentation allows each module type to be managed with appropriate arbitration strategies, ensuring real-time modules receive guaranteed bandwidth while non-real-time modules share remaining capacity, thus maintaining real-time performance in a cost-effective shared memory configuration.
Data Source
AI summary
A data processor that includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller and image data input units is disclosed. The components can be formed on a single semiconductor substrate. The display controller can perform display control on image data. The image data input unit stores the image data into a first area in the external memory. The image recognizing module or central processing unit executes an image process on the image data in the first area or image data in a second area, and stores a result of the process in a third area of the external memory.