Data Processor Address Mapping for Variable Memory Channels
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Solution Overview
Problem
Existing data processing systems with multiple memory channels face challenges in efficiently distributing memory traffic across varying numbers of channels, leading to potential bottlenecks and inefficiencies.
Innovation Solution
A two-stage address mapping process is employed, where memory addresses are first mapped to an intermediate address space, and then these intermediate addresses are mapped to the available memory channels, with the selection of the mapping operation based on the number of channels in use, ensuring efficient distribution of memory traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory addresses are directly mapped to memory channels without intermediate address space, then the mapping operation must change when the number of channels changes, but this increases device complexity and reduces adaptability
Solution Approach 1:
The patent introduces an intermediate address space that acts as a mediator between the original memory address and the memory channel. The address translation unit first translates the memory address to an intermediate address, then uses this intermediate address to select the memory channel. This intermediary mechanism allows the same translation operation to work regardless of the number of channels, eliminating the need to change mapping operations when channel configuration changes.
2Adaptability or versatility
If multiple mapping operations are maintained to handle different numbers of memory channels, then adaptability is improved, but device complexity and loss of information increase
Solution Approach 1:
The patent extracts the channel selection logic from the address translation operation itself. Instead of having the translation operation embed channel selection information that varies with channel configuration, the system separates these functions: the translation operation produces an intermediate address, and a separate channel selection unit uses this intermediate address to determine the appropriate memory channel. This extraction eliminates the need to maintain multiple mapping operations.
3Productivity
If the mapping operation changes based on the number of memory channels, then memory traffic distribution may be optimized, but system performance deteriorates due to bottlenecks from operation switching
Solution Approach 1:
The patent performs preliminary action by establishing a fixed address-to-intermediate-address translation operation that is independent of the number of memory channels. This translation is performed once and produces an intermediate address that inherently encodes channel selection information. By preparing this intermediate representation in advance, the system avoids the need to select and switch between multiple mapping operations during runtime, eliminating the time loss associated with operation switching while maintaining efficient memory traffic distribution.
Data Source
AI summary
In a data processing system in which varying numbers of channels for accessing a memory can be configured, the communications channel to use for an access to the memory is determined by mapping a memory address associated with the memory access to an intermediate address within an intermediate address space, selecting, based on the number of channels configured for use to access the memory, a mapping operation to use to determine from the intermediate address which channel to use for the memory access, and using the selected mapping operation to determine from the intermediate address which channel to use for the memory access.