Data Push Controller for Variable Length Payload Transfer
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Solution Overview
Problem
Current digital logic circuits face challenges in efficiently transferring large amounts of data, particularly with variable length payloads, as existing solutions like DMA require high processor utilization and latency, and TCP offload engines add unnecessary overhead, especially in point-to-point or multicast network topologies.
Innovation Solution
A format-agnostic data transfer circuit that includes a data push controller, interrupt generator, and buffer tracker, allowing for efficient transfer of both fixed and variable length data without relying on DMA, and minimizing processor overhead and latency by using hardware buffer tracking mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA is used for data transfer, then data transfer capability is improved, but processor utilization increases and latency increases for variable length payloads
Solution Approach 1:
The buffer tracker circuit automatically tracks buffer overflow conditions and generates interrupts without processor intervention. The system serves itself by having hardware monitor buffer status and trigger interrupts when thresholds are reached, eliminating the need for continuous processor monitoring of data transfer operations.
Solution Approach 2:
The buffer tracker acts as an intermediary between the data push controller and the processor. It monitors buffer conditions and generates interrupts only when necessary, mediating between the continuous data flow and the discrete processor attention, thereby reducing processor utilization while maintaining data transfer capability.
2Productivity
If TCP offload engine is used for variable length transfers, then data transfer is improved, but overhead increases and latency increases
Solution Approach 1:
The patent extracts only the essential buffer tracking and interrupt generation functionality from complex protocol engines like TCP offload. By taking out just the necessary elements (buffer monitoring, overflow detection, interrupt generation) and removing unnecessary protocol formatting overhead, the system achieves efficient variable length data transfer without the complexity of full TCP stack implementation.
Solution Approach 2:
Instead of using a complex protocol engine that adds formatting overhead and then stripping it away, the invention inverts the approach by directly implementing a simple buffer tracker that never adds the unnecessary formatting overhead in the first place. The system works backwards from the desired simple outcome rather than removing complexity from a complex solution.
3Ease of operation
If fixed length payload transfers are used, then processor knowledge of data amount is improved, but adaptability to variable length payloads deteriorates
Solution Approach 1:
The buffer tracker circuit provides universal functionality that works with both fixed and variable length payloads. It monitors buffer conditions and generates interrupts based on actual buffer status rather than predetermined fixed lengths, making the system adaptable to different payload types while maintaining ease of operation through automatic tracking.
Solution Approach 2:
The system transitions from static fixed-length assumptions to dynamic buffer tracking. The interrupt generation is dynamically adjusted based on actual buffer conditions and payload lengths, allowing the system to adapt to variable length payloads while maintaining the simplicity of knowing when data is ready for processing.
Data Source
AI summary
A format agnostic data transfer system and methods for transferring between disparate components can include a transmitting component having a data push controller, a receiving component having a processor, and a memory connected to the processor. The data push controller can receive configuration instructions from the receiving component processor transfer said data to said memory, without requiring the use of direct memory access (DMA) at said transmitting component. The reconfigurable nature of the data push controller can allow for both fixed and variable stream data to be sent, making the system data format agnostic. The receiving component can be a processor, while the transmitting component can be a field programmable gate arrays (FPGA) or an application specific integrated circuits (ASIC).


