Data Race Detection via CPU Register and Cache Metadata
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Solution Overview
Problem
Existing data race detection technologies suffer from significant performance overhead and high false positive rates, making them unsuitable for commercialization.
Innovation Solution
A method for detecting data races using a data race detection apparatus that records instruction information in a CPU's destination register, sets access log field information for a cache line, and utilizes this information to detect data races with low overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing data race detection technologies (TSAN, Inspector) are used, then data race detection capability is provided, but performance overhead increases significantly (12-200 times degradation)
Solution Approach 1:
The patent extracts only the essential information needed for data race detection (thread ID, memory address, access type) and stores it compactly in cache line metadata and CPU registers, rather than using comprehensive logging approaches. This selective extraction reduces overhead while maintaining detection capability.
Solution Approach 2:
The detection mechanism is segmented into two parts: cache line-level tracking using bitmap fields for fine-grained memory region tracking, and CPU register-level tracking for instruction-level precision. This segmentation allows efficient detection without requiring full system-wide instrumentation.
2Reliability
If existing data race detection technologies are used, then data race detection is achieved, but false positive rates increase
Solution Approach 1:
The patent performs preliminary actions by pre-initializing cache line metadata with thread ID and access type information before actual memory access occurs. This allows the system to compare incoming access patterns against pre-established baselines, reducing false positives by distinguishing legitimate concurrent accesses from actual data races.
Solution Approach 2:
The detection mechanism uses feedback by continuously monitoring memory access patterns and comparing them against recorded information in cache lines and registers. When a potential data race is detected, the system provides feedback through interrupts or exceptions, allowing for verification and reduction of false positives through contextual analysis.
3Measurement precision
If comprehensive memory access tracking is implemented, then detection accuracy improves, but device complexity increases
Solution Approach 1:
The patent makes the cache line structure universal by adding metadata fields (bitmap, thread ID, access type) that serve multiple functions: tracking memory access patterns, identifying owning threads, and detecting conflicts. This multi-functionality reduces the need for separate tracking structures, thereby reducing overall system complexity while maintaining high detection accuracy.
Solution Approach 2:
The cache lines and CPU registers serve themselves by automatically tracking and recording memory access information without requiring external monitoring infrastructure. The hardware itself maintains the detection state, eliminating the need for complex software agents or external debuggers, thus reducing system complexity while preserving measurement precision.
Data Source
AI summary
Disclosed herein are a data race detection method and apparatus. The data race detection method includes recording information about an instruction executed by a thread in a destination register in a Central Processing Unit (CPU) corresponding to the thread, setting information of an access log field corresponding to the instruction for a cache line of a cache memory, and detecting a data race using the information of the access log field and information of the destination register.