Data Rate Throttling in Internal Packet-Based Video Interfaces
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Solution Overview
Problem
Existing Timing Controller (TCON) technology for transporting video pixel streams in display devices is outdated, inefficient, and unable to meet modern requirements due to its complexity, high wire usage, and variable link rates proportional to pixel rates, leading to interoperability and cost-effectiveness issues.
Innovation Solution
A method for transmitting video pixel data from a transmitter to a receiver within a monitor using a balanced system with only two clock domains, where the receiver regenerates the pixel clock rate based on the link symbol clock frequency and predetermined M and N video values, reducing the number of clock domains and preventing overflow between buffers, and employing data rate throttling to adjust pixel rates and fit within available bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing TCON technology with variable link rates proportional to pixel rates is used, then the system can support different pixel rates, but the device complexity increases and interoperability becomes difficult
Solution Approach 1:
The patent applies parameter changes by using a fixed link rate instead of variable link rates proportional to pixel rates. The transmitter and receiver operate at a predetermined fixed link rate, and the pixel clock is regenerated at the receiver using a phase-locked loop (PLL) based on this fixed link rate. This eliminates the complexity of managing multiple clock domains while maintaining the ability to support different pixel rates through the fixed link infrastructure.
2Productivity
If many wires in parallel are used for video pixel stream transport, then high bandwidth is achieved, but the manufacturing cost and device complexity increase
Solution Approach 1:
The patent replaces the mechanical/wire-based parallel transmission system with a serial transmission system using a fixed link rate. Instead of using many wires in parallel to achieve high bandwidth, the invention uses a single link operating at a predetermined fixed rate, with data packed efficiently in serial form. This substitution dramatically reduces wire count and manufacturing complexity while maintaining transmission capacity.
3Adaptability or versatility
If the receiver maintains multiple clock domains to handle variable pixel rates, then flexibility is improved, but the receiver complexity and processing requirements increase
Solution Approach 1:
The patent applies self-service by enabling the receiver to autonomously regenerate the pixel clock from the fixed link rate using a phase-locked loop (PLL). Instead of requiring the receiver to maintain multiple clock domains or receive complex clock synchronization signals, the receiver independently generates the required pixel clock based on the predetermined fixed link rate and packet timing information embedded in the data stream. This self-service approach eliminates receiver complexity while maintaining flexibility.
4Adaptability or versatility
If LVDS with variable link rates is used, then interoperability between different display standards is achieved, but the system becomes slower and less efficient
Solution Approach 1:
The patent applies dynamics by using a fixed link rate for serial transmission that is optimized for speed and efficiency. Unlike variable LVDS link rates that scale with pixel rate and introduce timing variability, the fixed link rate provides a stable, high-speed transmission channel. The system dynamically adapts to different display standards through efficient packet packing and timing recovery rather than through variable link rates, thereby maintaining both speed and interoperability.
Data Source
AI summary
Methods and systems for transmitting video pixel data from a transmitter component, such as a controller, to a receiver within a monitor are described. Video data is received at a transmitter at an incoming pixel rate based on a pixel clock. The data is transmitted to the receiver at a link symbol clock rate and is drained from the receiver at the pixel clock rate, which is regenerated by the receiver using the link symbol clock frequency, an M video value, and an N video value. The M video value (Mvid) is determined by the transmitter based on the incoming pixel rate and the N video value (Nvid) may be constant. An accumulator is used within the transmitter to ensure that the transmitter and receiver create a balanced system.