Data Reading Circuit Phase Difference Detection
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Solution Overview
Problem
Current data reading methods across clock domains require additional hardware overheads and increased implementation complexity due to the need for extra I/O interfaces to determine phase differences between echo clock signals and local clock signals, which complicates data synchronization.
Innovation Solution
A data reading circuit with a phase difference determining module, time delay detection module, and reading control module that determines the phase difference between echo clock signals and local clock signals without additional I/O interfaces, allowing for precise data reading by identifying the optimal triggering edge based on calculated phase and time delay values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Data Sync signal is used to determine phase difference, then the phase difference can be determined, but hardware overheads increase due to additional I/O interfaces
Solution Approach 1:
The patent extracts the phase difference determination function from the external I/O interface and relocates it to the internal buffer. By using the existing buffer structure to detect phase differences between echo clock signals and local clock signals, the solution eliminates the need for additional Data Sync I/O interfaces, thereby reducing hardware overheads while maintaining measurement precision
Solution Approach 2:
The buffer serves dual purposes: it both stores data from the first clock domain and performs phase difference detection between clock signals. This self-service approach allows the buffer to determine phase differences internally without requiring external I/O interfaces, thus resolving the contradiction between measurement precision and device complexity
2Measurement precision
If a Data Sync signal is used to determine phase difference, then the phase difference can be determined, but implementation complexity increases due to strict phase relationship requirements
Solution Approach 1:
The patent removes the requirement for external Data Sync signal transmission and performs phase difference determination internally within the buffer using existing clock signals. This extraction eliminates the need to maintain strict phase relationships during external signal transmission, thereby reducing implementation complexity while preserving measurement precision
Solution Approach 2:
The buffer acts as an intermediary that processes both data and clock signals simultaneously, performing phase difference detection internally. This intermediary function eliminates the need for separate Data Sync signal paths and their associated phase relationship constraints, simplifying implementation while maintaining accurate phase difference determination
Data Source
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AI summary
Embodiments of the present invention disclose a data reading circuit, where the circuit is applied to a second clock domain. A first clock domain simultaneously sends data and an echo clock signal to the second clock domain. The data reading circuit includes a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain. By means of the present invention, a phase difference between an echo clock signal and a clock signal of a local domain can be determined, thereby implementing data reading.