Data Reading Device for Design-for-Testing with Masked Clock Edge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the design-for-testing technique, signal transmission speed variations in chip or circuit pins lead to data skew, making it difficult to accurately obtain test signals at high speeds, especially as communication specifications increase, reducing the available data valid window.
Innovation Solution
A data reading device and method incorporating a buffer and data serialization circuit that uses a trigger mask signal to mask one of the clock edge-triggered signals, extending the output time of test data from half to one clock cycle, thereby increasing the data valid window without altering internal chip data types or clock configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal transmission speed is increased to improve testing efficiency, then productivity is improved, but data skew increases and measurement precision deteriorates
Solution Approach 1:
The patent applies dynamics by making the clock edge selection adjustable and adaptive. The data serialization circuit can dynamically select between positive edge-triggered and negative edge-triggered clock signals based on the specific pin's characteristics, allowing the system to adapt to different transmission conditions while maintaining high speed and precision
Solution Approach 2:
The patent changes the parameter of clock edge selection (positive or negative) to optimize data output timing. By adjusting which clock edge triggers the data output, the system can compensate for data skew caused by different pin transmission characteristics, thereby extending the data valid window without reducing transmission speed
2Productivity
If clock frequency is increased to improve data output speed, then productivity is improved, but the available data valid window decreases
Solution Approach 1:
The system dynamically adjusts the clock edge selection based on the pin's transmission characteristics. This dynamic adaptation allows the system to maintain high clock frequencies while extending the data valid window by choosing the optimal clock edge (positive or negative) that provides sufficient setup and hold time for each specific pin
3Ease of operation
If testing circuit is added to facilitate testing, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The data serialization circuit serves multiple functions: it serializes data for high-speed transmission, selects between positive and negative clock edges to compensate for data skew, and provides a configurable interface for test machines. This multi-functionality reduces the need for separate dedicated testing circuits, thereby improving ease of operation without proportionally increasing device complexity
Solution Approach 2:
The patent introduces configurable parameters (clock edge selection, trigger mask signal) that allow the same circuit to adapt to different testing scenarios and pin characteristics. This configurability enables a single circuit design to handle diverse testing requirements, improving ease of operation without requiring multiple specialized circuits
Data Source
AI summary
A data reading device and a data reading method for design-for-testing are provided. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge-triggered signal, a clock negative edge-triggered signal, a trigger mask signal, and test data. The data serialization circuit masks one of the clock positive edge-triggered signal and the clock negative edge-triggered signal according to the trigger mask signal, and provides a part of the test data to an output terminal of the data serialization circuit as an output signal of the data reading device according to the unmasked one of the clock positive edge-triggered signal and the clock negative edge-triggered signal. Thus, a data valid window of the test data can be increased.