Data Receiver Voltage Compensation for BTI Stability

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Solution Overview

Problem

Miniaturized semiconductor apparatuses face deterioration due to Bias Temperature Instability (BTI), leading to decreased operation speed and shortened product life, particularly when transmitting data as single-ended signals without effective voltage level compensation.

Innovation Solution

A data receiving device is designed with a clock receiver and multiple data receivers that generate internal clock signals and data signals in synchronization, using a switching enable signal to adjust logic levels and compensate for voltage changes, thereby preventing mismatch and kick-back noise through differential amplification and noise compensation circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If miniaturized semiconductor apparatuses operate without voltage level compensation, then device complexity is reduced, but reliability deteriorates due to BTI-induced threshold voltage changes

Engineering Contradiction:
Improvecircuit structureVSAvoidoperation stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the reference voltage level based on the switching enable signal state. When the switching enable signal transitions, the reference voltage is compensated to counteract BTI-induced threshold voltage changes, thereby maintaining reliable operation without requiring complex structural modifications throughout the entire circuit.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The second data receiver performs self-service by automatically compensating for voltage level changes caused by BTI effects. The circuit monitors its own operation state and adjusts the reference voltage accordingly, eliminating the need for external intervention or complex compensation mechanisms from other parts of the system.

Inventive Principle:
Principle #25Self-service

2Device complexity

If single-ended signals are transmitted without differential amplification, then device complexity is reduced, but measurement precision deteriorates due to voltage level mismatches

Engineering Contradiction:
Improvesignal processing circuitVSAvoiddata reception accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary mechanism through the switching enable signal that mediates between the transmitted single-ended signal and the internal reference voltage. This intermediary controls the reference voltage compensation to ensure accurate data reception, allowing precise measurement without requiring complex differential amplification circuits for all signal paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The reference voltage parameter is dynamically changed based on the switching enable signal state to match the actual voltage levels in the single-ended signal transmission path. This parameter adjustment enables accurate data reception while keeping the overall circuit structure simple, avoiding the need for complex differential amplification throughout the entire signal path.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If clock signals are generated without synchronization control, then device complexity is reduced, but measurement precision deteriorates due to timing mismatches

Engineering Contradiction:
Improveclock generation circuitVSAvoiddata sampling accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements feedback by using the switching enable signal to control the reference voltage compensation timing. This feedback mechanism ensures that voltage level adjustments are synchronized with the clock signal transitions, maintaining precise timing relationships without requiring complex synchronization circuits in the clock generation path.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The reference voltage is preliminarily adjusted based on the switching enable signal state before data reception occurs. This preliminary action ensures that the correct voltage level is established in advance, enabling accurate data sampling without requiring complex real-time synchronization mechanisms during the data reception process.

Inventive Principle:
Principle #10Preliminary action

4Device complexity

If no voltage compensation is implemented, then device complexity is reduced, but loss of information increases due to kick-back noise

Engineering Contradiction:
Improvenoise compensation circuitVSAvoiddata integrity
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The patent converts the harmful kick-back noise effect into a beneficial mechanism by using the switching enable signal to trigger reference voltage compensation. The voltage level change that would normally cause kick-back noise is instead utilized to compensate for BTI effects, thereby protecting data integrity without requiring additional noise compensation circuits.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The second data receiver performs self-service by automatically compensating for voltage level changes that would otherwise cause kick-back noise and data errors. The circuit monitors its own operation state and adjusts the reference voltage accordingly, eliminating information loss without requiring external noise compensation mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20210241814A1Data receiving device, a semiconductor apparatus, and a semiconductor system using the data receiving device
Publication Date: 2021.08.05 SK HYNIX INC
  • US20210241814A1 patent drawing
  • US20210241814A1 patent drawing
  • US20210241814A1 patent drawing

AI summary

A data receiving device includes a clock receiver and a plurality of data receivers. The clock receiver is configured to generate a plurality of internal clock signals from a clock signal and a complementary clock signal based on a switching enable signal. The plurality of data receivers are configured to receive data and a reference voltage and compare the data with the reference voltage in synchronization with the plurality of internal clock signals, respectively, to generate first internal data. Among the plurality of data receivers, a data receiver receiving an internal clock signal, of which a logic level transitions signals when a logic level of the switching enable signal transitions, is configured to change a voltage level of the reference voltage when the logic level of the switching enable signal transitions.