Data Receiving Circuit Reducing Intersymbol Interference
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Solution Overview
Problem
Current memory apparatuses are ineffective in fully addressing intersymbol interference (ISI), which degrades signal quality due to bandwidth limitations in input data channels.
Innovation Solution
A data receiving circuit is designed with a comparator that amplifies voltage differences between input data and reference voltages, and multiple data paths that sample based on different clocks, using adjustment circuits to fine-tune signals based on previous bit data, thereby reducing ISI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback equalization adjustment circuits (CTLE or DFE) are used to compensate input data channel, then intersymbol interference is reduced, but circuit complexity increases
Solution Approach 1:
The data receiving circuit is divided into multiple independent data paths (first data path to M-th data path), where each path processes one bit of parallel data. Each data path contains its own adjustment circuit and sampling circuit, allowing independent optimization and reducing the complexity of any single path while maintaining overall signal quality through parallel processing.
Solution Approach 2:
The invention transitions from sequential serial data processing to parallel processing across multiple data paths. By converting the single-bit serial input into multi-bit parallel processing, the system achieves better ISI compensation through multiple simultaneous sampling operations, effectively adding a spatial dimension to the data reception process.
2Reliability
If multiple data paths with adjustment circuits are implemented, then ISI reduction effectiveness is improved, but circuit area increases
Solution Approach 1:
Multiple data paths share common components including a single comparator that amplifies voltage differences for all paths, shared reference voltage generation circuits, and common clock distribution networks. This merging of resources significantly reduces the total circuit area compared to having completely independent processing chains for each data path.
Solution Approach 2:
The adjustment circuits in each data path are designed with universal functionality, using the same structural blueprint adapted for different bit positions. Each adjustment circuit receives previous bit data and applies similar ISI compensation techniques, allowing standardized design that minimizes area while maintaining effectiveness across all paths.
3Productivity
If signal transmission rate and clock frequency are increased, then data transmission speed is improved, but intersymbol interference worsens due to bandwidth limitations
Solution Approach 1:
The adjustment circuits perform preliminary ISI compensation on the input data before the sampling circuits capture the signal. By pre-adjusting the voltage differences based on previous bit data, the system prepares the signal in advance to counteract the effects of high-speed transmission, ensuring that when sampling occurs at high clock frequencies, the signal quality remains intact despite the increased transmission rate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces the impact of ISI on current input data while minimizing circuit area and power consumption, thus enhancing memory performance without compromising storage capacity.
Implementation Method 1
the comparator is configured to amplify a voltage difference between the input data and the initial reference voltage and output double-ended signals as a result of the amplification
Implementation Method 2
the adjustment circuit is configured to adjust a voltage difference between the double-ended signals based on the previous second bit data to the previous N-th bit data to generate double-ended adjustment signals
Implementation Method 3
the sampling circuit is configured to, during a valid period of the i-th clock, compare and amplify a voltage difference between the double-ended adjustment signals based on the previous first bit data and output the i-th bit data
Data Source
AI summary
A data receiving circuit includes: a comparator for amplifying a voltage difference between input data and an initial reference voltage and outputting double-ended signals as a result of the amplification; and a plurality of data paths, each of the plurality of data paths receiving the double-ended signals, where an i-th data path is used to sample based on an i-th clock to obtain an i-th bit data, and the i-th data path includes: an adjustment circuit for adjusting a voltage difference between the double-ended signals based on a previous second bit data to a previous N-th bit data to generate double-ended adjustment signals; and a sampling circuit for comparing and amplifying, during a valid period of the i-th clock, a voltage difference between the double-ended adjustment signals based on the previous first bit data and outputting the i-th bit data.