Data Receiving Circuit Automatic Skew Adjustment
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Solution Overview
Problem
The existing semiconductor integrated circuits require manual and time-consuming skew adjustment processes for clock signals, increasing labor costs and prolonging the testing time before product shipment.
Innovation Solution
A data receiving circuit with a clock generation circuit, skew adjustment circuit, leading edge portion detecting circuit, and control circuit that automatically adjusts the delay time to synchronize the clock signal with the data signal, determining phase lead or lag to adjust the skew without human intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual skew adjustment process is performed for each semiconductor integrated circuit, then the clock signal synchronization is ensured, but the labor cost increases and the testing time is prolonged
Solution Approach 1:
The data receiving circuit automatically adjusts the skew of the clock signal relative to the data signal by using the delay circuit controlled by the control circuit, eliminating the need for manual adjustment. The circuit self-calibrates the timing alignment through the skew adjustment mechanism, achieving reliable synchronization without human intervention.
Solution Approach 2:
The delay circuit changes the delay time parameter dynamically to adjust the skew between the clock signal and data signal. By varying the delay time in response to detected phase relationships, the circuit achieves proper synchronization without manual intervention, resolving the contradiction between reliability and testing time.
2Reliability
If manual skew adjustment process is performed for each semiconductor integrated circuit, then the clock signal synchronization is ensured, but the labor cost increases
Solution Approach 1:
The data receiving circuit performs automatic skew adjustment through its internal control mechanism, eliminating the need for manual operation. The control circuit autonomously determines phase relationships and adjusts the delay circuit accordingly, making the system operationally simple while ensuring reliable synchronization.
Solution Approach 2:
The leading edge portion detecting circuit provides feedback about the phase relationship between the clock signal and data signal to the control circuit. This feedback loop enables the control circuit to automatically adjust the delay circuit, ensuring proper synchronization without manual intervention and reducing operational complexity.
3Productivity
If automatic skew adjustment is implemented, then the testing time is reduced, but the device complexity increases
Solution Approach 1:
The skew adjustment function is segmented into distinct functional blocks: the delay circuit for timing adjustment, the leading edge portion detecting circuit for phase detection, and the control circuit for coordination. This segmentation allows each component to perform its specific function efficiently, achieving automatic adjustment while keeping the overall complexity manageable through modular design.
Solution Approach 2:
The data receiving circuit integrates multiple functions including data reception, clock signal generation, phase detection, and skew adjustment within a single integrated structure. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving automatic testing and adjustment capabilities.
Data Source
AI summary
A data receiving circuit includes a clock generation circuit, a skew adjustment circuit, a leading edge detecting circuit, and a control circuit. The clock generation circuit generates a clock signal and a decision clock signal transitioning from a second level to a first level at a time point advancing by a time of ½ of the bit cycle with respect to the clock signal, according to the received reference clock signal. The skew adjustment circuit generates a skew adjustment data signal by delaying the received data signal through a delay circuit. The leading edge detecting circuit detects a leading edge of one bit of the skew adjustment data signal to generate a leading edge detection signal. The control circuit controls the delay time of the delay circuit based on the decision clock signal and the leading edge detection signal.