Data Reception Apparatus Oversampling Clock Error Compensation
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Solution Overview
Problem
Current data communication systems face challenges in achieving short lock times due to clock frequency errors between data transmission and reception sides, particularly in CDR with phase interpolator and phase synchronization, where existing methods like oversampling and digital processing are insufficient to significantly shorten lock times.
Innovation Solution
A data reception apparatus is designed with a separate receive-side clock source that generates oversampling data and calculates an integrated number of samples per bit, using an approximated line to determine bit length accurately, thereby mitigating the effects of clock frequency errors and other degradation factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If CDR with phase interpolator is used to achieve short lock time, then lock time is reduced, but clock frequency error between transmit and receive sides must be kept very small
Solution Approach 1:
The patent replaces the analog phase interpolator mechanism with a digital signal processing approach. By oversampling the received signal and using digital correlation processing, the system achieves phase detection and frequency offset compensation without requiring precise analog phase interpolation, thereby eliminating the strict clock frequency error requirement while maintaining short lock time performance
Solution Approach 2:
The patent changes the sampling rate parameter by using oversampling (sampling at a rate higher than the Nyquist rate). This parameter change allows the system to capture more signal information and use digital processing to compensate for frequency offsets, resolving the contradiction between short lock time and clock frequency error tolerance
2Measurement precision
If CDR with phase synchronization is used to achieve frequency error compensation, then clock frequency error tolerance is improved, but lock time becomes excessively long
Solution Approach 1:
The patent performs oversampling (excessive sampling beyond the minimum required) and uses digital processing to achieve both frequency offset compensation and phase synchronization simultaneously. This partial implementation of full phase synchronization provides frequency tolerance with significantly reduced lock time by not requiring complete phase alignment before data recovery
3Loss of time
If oversampling and digital processing are used to shorten lock time, then lock time is reduced, but the method is insufficient to significantly reduce lock time with clock frequency errors
Solution Approach 1:
The patent implements a feedback mechanism where the received signal is oversampled, correlated with a local replica, and the phase/frequency offset is estimated and compensated in a feedback loop. This feedback approach enables accurate data determination even in the presence of clock frequency errors while achieving significantly reduced lock time compared to conventional methods
Data Source
AI summary
A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).