Data Recovery Circuit Using Multi-Phase Sampling and Logic Operations
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Solution Overview
Problem
In high-speed data transmission, serial interfaces face challenges with clock signal and data skew due to short unit intervals and long transmission distances, leading to errors in data recovery, which existing technologies struggle to address effectively.
Innovation Solution
A data recovery circuit that samples data using multiple sampling clock signals with different phases, performs logic operations to generate intermediate recovery data, and uses CRC checks to output error-free data, employing XOR gates, OR gates, CRC checkers, frame buffers, and error correction units to ensure accurate data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a serial interface is used for high-speed data transmission, then data transmission rate is improved, but clock signal and data skew occurs leading to recovery errors
Solution Approach 1:
The patent segments the data recovery process into multiple parallel paths, each processing sampled data at different phase positions. By dividing the recovery task into multiple segments that can be independently processed and then combined, the system achieves both high-speed processing and accurate error detection through redundant sampling paths.
Solution Approach 2:
The patent changes the phase parameter of sampling clock signals to create multiple versions of sampled data. By varying the phase parameter of the sampling clocks, the system captures data at different points in the signal cycle, enabling error detection and correction while maintaining high transmission rates.
2Reliability
If multiple sampling clock signals with different phases are used, then data recovery accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent merges multiple sampled data paths by performing logical operations (XOR, OR) on the parallel data streams. This combining process integrates the information from multiple phase-sampled paths into intermediate recovery data, achieving error detection and correction while consolidating the complex parallel processing into a unified output structure.
Solution Approach 2:
The patent creates multiple copies of the sampling and processing circuitry operating in parallel with different phase shifts. By replicating the essential processing functions across multiple copies that process the same input data at different phases, the system achieves enhanced reliability through redundancy while using standardizable circuit blocks.
3Reliability
If logic operations are performed on sampled data to generate intermediate recovery data, then error detection capability is improved, but processing time increases
Solution Approach 1:
The patent employs periodic logical operations on the sampled data streams, where XOR and OR operations are systematically applied in a repeating pattern across the parallel data paths. This periodic processing structure enables continuous error detection without requiring complete processing of all data before beginning error checking, thus reducing overall processing time while maintaining detection capability.
Data Source
AI summary
In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.