Data Recovery Circuit Using Oversampling to Cut SerDes Complexity
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Solution Overview
Problem
High-speed IO data communication systems face challenges with SerDes technology due to its complexity, large layout area, and high power consumption.
Innovation Solution
A data recovery circuit comprising clock generation, data reception, data oversampling, and data selection circuits, which reduces layout area and power consumption by using a simple structure for data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SerDes is used for data recovery, then data recovery function is achieved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential data recovery function from the complex SerDes system, implementing a simplified dedicated data recovery circuit that performs clock generation, data reception, oversampling, and selection without the full SerDes functionality, thereby reducing device complexity while maintaining data recovery capability
Solution Approach 2:
The data recovery circuit is segmented into four independent functional modules: clock generation circuit, data reception circuit, data oversampling circuit, and data selection circuit. This segmentation allows each module to perform its specific function with minimal complexity, avoiding the need for a monolithic complex SerDes structure
2Reliability
If SerDes is used for data recovery, then data recovery function is achieved, but layout area increases
Solution Approach 1:
The patent extracts only the essential data recovery function from the complex SerDes system, implementing a simplified dedicated data recovery circuit that performs clock generation, data reception, oversampling, and selection without the full SerDes functionality, thereby reducing device complexity while maintaining data recovery capability
Solution Approach 2:
The patent merges multiple functions into a single integrated data recovery circuit structure, where the clock generation, data reception, oversampling, and selection functions are combined in one compact circuit block, reducing the overall layout area compared to separate SerDes modules
3Reliability
If SerDes is used for data recovery, then data recovery function is achieved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential data recovery function from the complex SerDes system, implementing a simplified dedicated data recovery circuit that performs clock generation, data reception, oversampling, and selection without the full SerDes functionality, thereby reducing device complexity while maintaining data recovery capability
Solution Approach 2:
The data oversampling circuit dynamically samples incoming data at multiple points within each clock cycle to capture the optimal data value, allowing the circuit to adapt to signal variations and achieve reliable data recovery with lower power consumption compared to continuous high-speed SerDes operation
Data Source
AI summary
A circuit and method for data recovery comprises clock generation, data reception, data oversampling, and data selection circuits; wherein, clock generation circuits are used to output data reception clock signals and data processing clock signals; data reception circuits are used to receive original transmission data from the data transmitter in accordance with the data reception clock signals, and transmit data based on its output; data oversampling circuits are used for multiple oversampling of at least one bit of transmission data corresponding to at least one data processing cycle according to the data processing clock signal and outputting corresponding parallel sample data; data selection circuits are used for transition detection on the corresponding parallel sample data for each data processing cycle and selecting sample data from the corresponding parallel sample data to output based on the transition detection results. The embodiments of the present application use a simple structure to implement data recovery, reducing layout area and circuit power consumption.