Data Recovery Timing Selection for Parallel Bus Interference
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Solution Overview
Problem
In parallel electrical bus systems, inter-symbol interference degrades signal integrity, leading to reduced reliability and performance, as the timing relationship between the data and clock/strobe signals is adversely affected by factors like reflections and mis-termination, necessitating lower symbol rates to maintain signal validity.
Innovation Solution
A data recovery system dynamically selects a timing reference signal based on the symbol history of the data signal, ensuring that both signals incur identical inter-symbol interference effects, thereby maintaining their relative timing and compensating for interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock or strobe provides timing reference for many data wires on parallel bus, then device complexity is reduced, but signal integrity deteriorates due to timing relationship degradation from reflections, over-dampening, and simultaneous switching effects
Solution Approach 1:
The patent segments the timing reference function by providing each data wire with its own dedicated clock or strobe signal rather than sharing a single clock across multiple wires. This segmentation isolates the timing reference for each data line, preventing interference from reflections and simultaneous switching effects that occur when multiple wires share a common clock distribution network.
Solution Approach 2:
The patent introduces an intermediary element - the data-driven clock generation mechanism - where each data line's own transitions drive its dedicated clock signal. This intermediary approach eliminates the need for complex external clock distribution while ensuring each data wire has a timing reference that is inherently synchronized to its own signal characteristics, thereby maintaining signal integrity without requiring complex clock distribution infrastructure.
2Reliability
If driver pre-compensation is implemented to compensate for inter-symbol interference, then signal integrity is improved, but device complexity increases due to required careful modeling of driver, transmission line, and receiver
Solution Approach 1:
The patent implements self-service by having each data line generate its own clock signal from its own data transitions. The data-driven clock generation uses the data line's own edge transitions to trigger the clock, automatically adapting to the actual signal conditions without requiring external modeling or pre-compensation circuits. This self-service mechanism inherently compensates for inter-symbol interference and transmission line effects without adding complex pre-compensation logic.
Solution Approach 2:
The patent performs preliminary action by generating the clock signal in advance based on expected data transitions. The data-driven clock is generated ahead of time using the data line's own transition history, allowing the receiver to be pre-synchronized to the incoming data signal characteristics before actual data sampling occurs, thereby compensating for anticipated signal degradation without complex real-time adjustment circuits.
3Reliability
If symbol rate is reduced to widen timing eye for reliable sampling, then signal integrity is maintained, but productivity decreases due to lower data transmission rate
Solution Approach 1:
The patent applies dynamics by making the clock timing adaptive to actual data signal conditions rather than using a fixed, conservative timing reference. The data-driven clock dynamically adjusts its timing based on the actual edge transitions of each data line, allowing the system to operate at higher symbol rates by accurately tracking the actual signal timing rather than relying on widened, conservative timing eyes that limit transmission rate.
Data Source
AI summary
Systems, methodologies, media, and other embodiments associated with data recovery are described. One exemplary system embodiment includes a sampling logic configured to sample data from a data line using a timing reference that is selectable from a plurality of timing reference signals. The system may also include a symbol history logic configured to track a symbol history of the data sampled by the sampling logic and a timing selection logic configured to select the timing reference used to sample the data based on the symbol history of the data to compensate for inter-symbol interference.