Multi-Domain Data Retention Latch for Low-Leakage Power Down
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Solution Overview
Problem
Existing electronic circuits face challenges in efficiently retaining data bits during power down modes to conserve energy, as current methods lack flexibility in power supply voltage levels, leading to increased power consumption and leakage currents.
Innovation Solution
A data retention circuit utilizing a master latch, slave latch, and retention latch operating in different power domains with distinct power supply voltage levels, along with a level shifter to shift logical levels between domains, allowing for data retention during power down modes with reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data bits are saved using latch circuits during power down events, then data continuity is maintained, but power consumption increases and battery life is reduced
Solution Approach 1:
The circuit is divided into multiple power domains (first power domain with first voltage level, second power domain with second voltage level) that can be independently powered down. This segmentation allows selective power management where only necessary domains remain active, reducing overall power consumption while maintaining data continuity through the retention latch circuit that bridges power domain transitions.
Solution Approach 2:
The patent utilizes different voltage levels (first voltage level vs. second voltage level) as a parameter to enable power management. By transitioning between these voltage levels and using a level shifter, the circuit can enter low-power states while preserving data, thus reducing power consumption without sacrificing reliability.
2Reliability
If traditional latch circuits are used for data retention, then data is preserved during power down, but leakage currents increase
Solution Approach 1:
The retention latch circuit is placed in a separate second power domain that can be independently controlled from the first power domain. This allows the retention function to remain active while the main circuitry is powered down, minimizing leakage currents in the inactive domains while preserving data integrity.
Solution Approach 2:
The level shifter acts as an intermediary between the first and second power domains, enabling voltage level translation during power transitions. This intermediary component facilitates clean power domain isolation, reducing leakage paths while maintaining data retention capability through the retention latch.
3Ease of manufacture
If power supply voltage levels are fixed, then circuit design is simplified, but flexibility in circuit applications is reduced
Solution Approach 1:
The patent implements dynamic voltage level management where the circuit can operate at different voltage levels (first voltage level or second voltage level) depending on power domain states. The level shifter dynamically adapts voltage levels during transitions, providing flexibility for various circuit applications while maintaining a relatively simple overall design structure.
Solution Approach 2:
The retention latch circuit and level shifter combination serves multiple functions: data retention during power down, voltage level translation, and enabling different operating modes. This multi-functional approach increases adaptability for various circuit applications without significantly complicating the design.
Data Source
AI summary
A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.