Multi-Domain Data Retention Latch for Power-Down Integrity
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Solution Overview
Problem
Existing data retention circuits in electronic circuits face challenges in maintaining data integrity during power down cycles, particularly when different power domains require different voltage levels, leading to inefficiencies in energy consumption and circuit flexibility.
Innovation Solution
A data retention circuit design that includes a master latch, slave latch, and retention latch operating in separate power domains with distinct voltage levels, utilizing level shifters to transition data between these domains, allowing data retention during power down cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data retention circuits use a single power domain with uniform voltage levels, then circuit design is simpler, but flexibility in power management and energy efficiency are reduced
Solution Approach 1:
The circuit is divided into multiple power domains (first power domain with first voltage level, second power domain with second voltage level) that can be independently controlled. This segmentation allows different portions of the circuit to operate at different voltage levels, enabling flexible power management while maintaining data retention across power transitions.
Solution Approach 2:
Level shifters are introduced as intermediary components between the first and second power domains. These level shifters translate voltage levels and control signals between domains, enabling coordinated operation and data transfer while maintaining the independence and flexibility of each power domain.
2Use of energy by moving object
If power down cycles are implemented to conserve energy, then energy efficiency improves, but data integrity during transitions becomes challenging
Solution Approach 1:
The retention latch is configured to capture and hold data bits before power down cycles occur in the first power domain. By performing this preliminary data capture action, the circuit ensures data integrity is maintained throughout subsequent power transitions, allowing energy-efficient power cycling without compromising reliability.
Solution Approach 2:
The second power domain is designed to remain powered on continuously while the first power domain undergoes power down cycles. The retention latch in the second power domain maintains continuous operation to hold data bits, ensuring uninterrupted data retention functionality throughout the power management cycle.
3Loss of energy
If separate power domains with different voltage levels are used, then power management flexibility and energy efficiency improve, but circuit complexity increases
Solution Approach 1:
Different voltage levels are assigned to different power domains based on their specific functional requirements. The first power domain operates at a first voltage level optimized for its operations, while the second power domain operates at a second voltage level optimized for data retention. This local optimization reduces overall power consumption while managing complexity through functional specialization.
Data Source
AI summary
A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.