Data Router Direct Host Memory Access via Address Control Structures
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Solution Overview
Problem
Existing input/output processing systems require data to be stored in local channel memory for error checking, leading to increased response times and reduced I/O start rates due to the need for store and forward operations between the host computer and host bus adaptor (HBA).
Innovation Solution
A data router in the channel subsystem allows the HBA to directly access host memory by generating and using address control structures that include Offset and Expected Offset fields for data transfer requests, enabling direct data transfer and error checking without storing data in local channel memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in local channel memory for error checking, then reliability is improved, but response time increases and I/O start rates decrease
Solution Approach 1:
The patent extracts the data storage function from local channel memory by enabling direct access to host memory. The HBA can now access host memory directly without storing data in local channel memory, eliminating the store-and-forward delay while maintaining error checking capabilities through alternative mechanisms.
Solution Approach 2:
The patent introduces address control structures (ACWs) as intermediaries that enable the HBA to directly access host memory. These ACWs contain addressing information that allows the HBA to locate and access data in host memory without requiring intermediate storage in local channel memory, thus reducing response time while maintaining reliability.
2Reliability
If data is stored in local channel memory for error checking, then reliability is improved, but I/O start rates are reduced
Solution Approach 1:
The patent removes the requirement to store data in local channel memory by enabling direct HBA access to host memory. This extraction of the intermediate storage step eliminates the bottleneck that limited I/O start rates, allowing multiple I/O operations to initiate simultaneously without being constrained by local memory capacity and access speeds.
Solution Approach 2:
The patent employs preliminary action by pre-establishing address control structures that contain all necessary addressing information before data transfer begins. This allows the HBA to immediately access host memory without waiting for data to be staged in local channel memory, thereby increasing I/O start rates while maintaining error checking through the pre-configured address structures.
3Loss of time
If direct access to host memory is enabled, then response time decreases and I/O start rates increase, but system complexity increases
Solution Approach 1:
The patent uses address control structures as intermediaries to manage the complexity of direct HBA access to host memory. These ACWs serve as a standardized interface that abstracts the complex addressing requirements, providing a systematic method for the HBA to locate and access data in host memory without requiring complex control logic in the HBA itself.
Solution Approach 2:
The patent changes the addressing parameters by introducing Offset fields and Expected Offset fields in the address control structures. These parameter changes enable the HBA to directly calculate host memory addresses without complex translation logic, simplifying the addressing mechanism while enabling fast direct access to host memory and improving response time.
Data Source
AI summary
A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW.