Data Sampler Phase Control for Pattern-Dependent Jitter

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

As data rates for SerDes increase, the time window for accurate sampling of waveforms decreases, making it challenging to find a consistently clean sampling point due to edge jitter, particularly caused by power supply variations affecting clock timing in the transmitter, which existing techniques address expensively by requiring robust power supplies and increased silicon area.

Innovation Solution

A data sampling and clock recovery circuit with a phase detector and data sample analyzer that adjusts the clock signal phase based on detected phase differences and data patterns, using a phase interpolator and multiplexer to select optimal sampling phases, thereby compensating for power supply-induced jitter without increasing implementation costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data rate is increased to 20 Gbps, then productivity is improved, but the time window for accurate sampling decreases to maximum 50 ps making reliable sampling difficult

Engineering Contradiction:

Improvedata rateVSAvoidsampling time window

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent adjusts the sampling phase dynamically based on detected data patterns. The data sampler is positioned at different phases relative to the clock signal depending on the detected pattern, allowing optimal sampling within the compressed 50 ps window at 20 Gbps data rates

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

A data pattern detector detects patterns in received data and generates control signals that adjust the sampling phase. This feedback mechanism allows the system to adapt to pattern-dependent jitter and maintain accurate sampling at high data rates

Inventive Principle:

Principle #23Feedback

2Reliability

If robust power supply with low ripple (30 mV or less) is used to minimize deterministic jitter, then reliability is improved, but device complexity and cost increase significantly

Engineering Contradiction:

Improvedeterministic jitter controlVSAvoidpower supply requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Instead of trying to eliminate power supply ripple through complex power supply design, the patent detects the pattern-dependent jitter caused by power supply variations and compensates for it by adjusting the sampling phase. This converts the harmful effect into a manageable parameter

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent replaces the mechanical/electrical solution of improving power supply stability with a signal processing solution. Rather than fixing the power supply to reduce jitter, the system detects the jitter pattern and compensates through phase adjustment of the sampler

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8120395B2Use of data decisions for temporal placement of samplers

Publication Date: 2012.02.21 TEXAS INSTRUMENTS INC

AI summary

A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected position of the edges. A further correction to the sampling position is made in response to the recent history of the data received. The correction is modelled on predictable jitter, for example, that in a transmitter caused by changes in data causing the supply voltage to drop.