Data Sampling Circuit Phase Selection for DDR5
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Solution Overview
Problem
Current data sampling circuits in DRAMs face challenges in accurately identifying phase information and rapidly testing bit error rates due to phase uncertainty caused by clock dividers, which affects the reliability and efficiency of data transmission in high-speed DDR5 memory systems.
Innovation Solution
A data sampling circuit comprising a frequency dividing circuit, a sampling circuit, and a selection circuit that processes data sampling signals to obtain multiple signals associated with respective phases, and selects target signals based on preamble information and Mode Register Set (MRS) information, enabling accurate phase identification and bit error rate testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency dividing circuit is used to generate multiple phase signals, then the data transmission speed can be increased, but phase uncertainty occurs making it difficult to accurately identify phase information
Solution Approach 1:
The patent applies preliminary action by performing phase identification during a preamble period before actual data transmission. The selection circuit identifies the correct phase signal among multiple divided signals during this preliminary time window, ensuring accurate phase selection is established before high-speed data transfer begins, thus resolving the phase uncertainty issue while maintaining high transmission speed
Solution Approach 2:
The patent introduces an intermediary selection circuit that acts as a mediator between the frequency dividing circuit and the sampling circuit. This selection circuit receives multiple phase-divided signals, identifies the correct phase through comparison with reference signals, and selects the appropriate signal for subsequent data transmission, thereby eliminating phase uncertainty without reducing transmission speed
2Adaptability or versatility
If multiple phase signals are generated for DDR5 memory, then data transmission capability is enhanced, but the complexity of testing and identifying the correct phase increases
Solution Approach 1:
The patent applies self-service by enabling the selection circuit to automatically identify and select the correct phase signal through self-comparison with reference signals during the preamble period. This self-identifying mechanism eliminates the need for external complex testing equipment or manual phase identification processes, reducing testing complexity while maintaining enhanced data transmission capability
Solution Approach 2:
The patent implements feedback by comparing the multiple phase-divided signals against reference signals and using the comparison results to control the selection circuit. This feedback mechanism automatically determines which phase signal is correct and directs subsequent data transmission accordingly, simplifying the overall testing and identification process while supporting advanced DDR5 transmission modes
Data Source
AI summary
A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.