Data Scanning Circuit Dynamic Rule Length Configuration
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Solution Overview
Problem
Existing data scanning circuits are inefficient due to the need to scan all content of packet data, leading to increased circuit complexity and wasted resources, as they are not flexible enough to handle rules of varying lengths, resulting in delayed processing and potential system poisoning from viruses or advertisements.
Innovation Solution
A data scanning circuit comprising a memory circuit, operational circuit, and decision circuit that dynamically configures the length of scanning rules, using programmable codes and logic operations to efficiently identify data satisfying scanning rules, reducing circuit complexity and enhancing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all packet data content is scanned sequentially to ensure no scanning loss, then scanning completeness is improved, but scanning time increases and processing speed decreases
Solution Approach 1:
The patent segments the scanning task by dividing packet data into multiple blocks that can be processed in parallel by multiple comparators simultaneously. Each comparator handles a specific block, allowing concurrent scanning operations that reduce total scanning time while maintaining complete coverage through systematic block division and parallel processing.
2Adaptability or versatility
If fixed-size rules are used to handle variable-length scanning rules, then compatibility is improved, but cache space is wasted and circuit complexity increases
Solution Approach 1:
The patent implements dynamic rule length configuration where the rule length can be adjusted according to actual scanning needs. The system uses configurable parameters that allow the scanning circuit to adapt its rule length dynamically, avoiding the waste of fixed-size cache spaces and reducing circuit complexity by only allocating resources needed for the current scanning task.
3Reliability
If multiple comparators scan all packet data sequentially, then scanning thoroughness is improved, but circuit area increases and processing efficiency decreases
Solution Approach 1:
The patent divides packet data into multiple blocks and assigns different comparators to scan different blocks simultaneously. This segmentation enables parallel processing where multiple comparators work concurrently on different data segments, maintaining thorough scanning coverage while reducing the effective circuit area needed at any given moment compared to sequential scanning of entire data.
Solution Approach 2:
The patent transitions from sequential one-dimensional scanning to parallel multi-dimensional scanning by organizing comparators to process different data blocks simultaneously. This dimensional change in processing architecture allows multiple scanning operations to occur in parallel time slices, improving throughput while managing circuit resource utilization more efficiently.
Data Source
AI summary
The present invention relates to a data scanning circuit and method. According to the present invention, a memory circuit stores a plurality of codes. Each of the code corresponds to a sub-rule. The memory circuit outputs at least first bit and at least second bit of each code, respectively, according to a first and a second data items. An operational circuit performs logic operations on the first and second bits, and produces an operated result. A decision circuit decides whether the input data satisfies the scanning rule according to the operated result.