Memory Device Refresh Control for Data-Selective Power Reduction
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Solution Overview
Problem
Volatile memory devices like DRAM experience significant power consumption due to frequent refresh operations to maintain cell charges, which are lost due to leakage currents, especially when word lines transition frequently, affecting adjacent cells.
Innovation Solution
A memory device with a refresh control circuit that skips refresh operations if data is '0' and performs refresh only if data is '1', utilizing a data sensing circuit to determine the state and control the sense amplification circuit accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed repeatedly to prevent cell charge loss, then data reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies partial action by performing refresh operation selectively only when necessary (when data is '1' or when cell charge loss is detected) rather than refreshing all memory cells continuously. The refresh control circuit determines whether to perform refresh based on data state, thereby reducing unnecessary refresh operations and lowering power consumption while maintaining data reliability for cells that actually need it.
2Speed
If word line transitions frequently between active and precharge states, then data access speed is improved, but cell charge loss in adjacent memory cells increases
Solution Approach 1:
The patent applies preliminary anti-action by performing refresh operation on memory cells before their charge is completely lost due to frequent word line transitions. The refresh control circuit proactively detects cells that need refreshing and performs refresh operations in advance, preventing data corruption caused by charge loss from adjacent cell interference during frequent word line switching.
Data Source
AI summary
An example memory device includes a memory cell connected with a bit line, an equalization circuit connected with the bit line and a complementary bit line, a data sensing circuit connected with at least one of the bit line or the complementary bit line, where the data sensing circuit is configured to sense data in the memory cell and to output a data sense signal, a sense amplification circuit connected with the bit line and the complementary bit line, where the sense amplification circuit is configured to perform a refresh operation on the memory cell, and a refresh control circuit configured to receive the data sense signal and to control the refresh operation of the sense amplification circuit. Based on the data of the memory cell being “0”, the refresh control circuit is configured to output a first control signal such that the sense amplification circuit skips the refresh operation.