Data Selector Circuit Timing Adjustment for Display Noise
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Solution Overview
Problem
In liquid crystal displays, the use of NMOS transistors in data selector circuits leads to varying rising speeds of output signals based on input signal polarities, causing potential variations in the common electrode and generating noise in the display panel.
Innovation Solution
Incorporating timing adjustment switches connected in parallel with time division switches, which are turned on earlier than the time division switches by a predetermined period to synchronize the rising of positive and negative precharge and written voltages, thereby reducing voltage differences across the common electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NMOS transistors are used as time division switches in the data selector circuit, then the circuit can achieve fast switching operation, but the rising speeds of output signals become different depending on polarities of input signals, causing potential variations in the common electrode and generating noise
Solution Approach 1:
The patent applies preliminary action by turning on the timing adjustment switches earlier than the time division switches by a predetermined period. This advance activation allows the output signals to start rising before the main switching event, compensating for the polarity-dependent rising speed differences of NMOS transistors and preventing common electrode potential variations that would otherwise generate noise.
Solution Approach 2:
The patent implements dynamics by introducing adjustable timing control for different switch groups. The timing adjustment switches have independently controllable turn-on timings that can be dynamically optimized based on the polarity of input signals. This dynamic timing adjustment equalizes the rising speeds of output signals regardless of input polarity, thereby eliminating the noise generation mechanism while preserving the fast switching capability of NMOS transistors.
2Object-generated harmful factors
If timing adjustment switches are added to synchronize signal rising, then noise generation is suppressed, but the device complexity increases
Solution Approach 1:
The patent applies merging by integrating the timing adjustment switches in parallel with the existing time division switches within the same switch groups. This combined configuration allows both the original time division function and the timing adjustment function to be performed by a unified circuit structure, reducing overall complexity compared to having separate independent timing adjustment circuits.
Solution Approach 2:
The timing adjustment switches serve multiple functions: they provide timing compensation for polarity-dependent rising speed differences, act as additional conduction paths to equalize signal levels, and work cooperatively with the time division switches to achieve both time-division multiplexing and noise suppression. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Data Source
AI summary
A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.