Data Sensing Circuit Offset Reduction via Transistor Parameter Adjustment

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Solution Overview

Problem

Conventional data sensing circuits in memory devices face challenges in accurately sensing data due to transistor offset and require increased capacitance or driving voltage, which can enlarge the circuit area and increase current consumption.

Innovation Solution

The implementation of a data sensing circuit using NMOS and PMOS transistors for each bit line to supply pull-up and pull-down voltages respectively, allowing for improved voltage amplification and reduced offset, while being strategically placed at the center of the cell array to enhance sensing margin and integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If capacitance of the memory cell is increased to reduce offset, then offset is reduced, but area of the bit line sense amplifier increases

Engineering Contradiction:

Improvesensing precisionVSAvoidarea of bit line sense amplifier

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent changes the voltage parameter by applying different gate voltages to NMOS and PMOS transistors in the sense amplifier. Specifically, it adjusts the gate voltage of the PMOS transistor to compensate for threshold voltage mismatches, thereby reducing offset without increasing capacitance or area.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If driving voltage level of the bit line sense amplifier is increased to reduce offset, then offset is reduced, but current consumption increases

Engineering Contradiction:

Improvesensing precisionVSAvoidcurrent consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent optimizes the driving voltage levels by carefully selecting gate voltages for the NMOS and PMOS transistors. This allows the sense amplifier to achieve low offset through voltage parameter adjustment rather than increasing overall driving voltage, thus maintaining low current consumption.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If transistors are fabricated with different characteristics, then manufacturing flexibility is improved, but offset in operation increases

Engineering Contradiction:

Improvemanufacturing flexibilityVSAvoidsensing precision

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the gate voltage of the PMOS transistor is adjusted based on the detected offset condition. This feedback loop compensates for transistor characteristic variations, maintaining sensing precision despite manufacturing tolerances.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts voltage parameters to compensate for transistor mismatches. By changing the gate voltage of the PMOS transistor in response to offset conditions, it compensates for fabrication variations without requiring precise matching of transistor characteristics.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9159384B2Data sensing circuit and memory device including the same

Publication Date: 2015.10.13 SK HYNIX INC

AI summary

An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.