Data Sequencing Circuit for Reduced-Toggle Memory Transfers
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Solution Overview
Problem
Existing memory arrays face challenges in efficiently performing computations due to high power consumption and circuit complexity when data bits are moved between memory arrays and computation circuits, particularly in computing-in-memory operations where consecutive data elements often have the same-valued MSBs and LSBs, leading to increased signal toggling rates.
Innovation Solution
A data sequencing circuit that transmits bits of data elements in alternating sequence order, ensuring adjacent bits are either MSBs or LSBs, reducing signal toggling rates and power consumption by using an input circuit, storage element, multipliers, an adder, and an accumulator configured to perform operations in alternating sequence orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data bits are moved between memory arrays and computation circuits in conventional sequence order, then data processing can be performed, but signal toggling rates increase and power consumption rises
Solution Approach 1:
The patent applies dynamics by making the data transmission sequence adaptive rather than fixed. The sequencing circuit dynamically adjusts the bit transmission order based on the actual data values being processed. When consecutive data elements have the same MSB or LSB, the circuit switches between MSB-first and LSB-first transmission sequences, creating a dynamic response that reduces signal toggling and power consumption while maintaining processing efficiency.
Solution Approach 2:
The patent changes the parameter of transmission sequence order based on data characteristics. By detecting whether consecutive data elements have identical MSBs or LSBs, the system switches between different transmission sequences (MSB-first vs. LSB-first), thereby changing the transmission parameter to optimize power consumption without sacrificing processing productivity.
2Productivity
If conventional data transmission sequences are used, then data can be processed, but circuit complexity increases due to additional sequencing logic
Solution Approach 1:
The patent merges the sequencing function with the existing data transmission path by integrating a sequencing circuit that shares control signals with the computation circuitry. The sequencing logic is combined with the data bus control mechanisms, allowing the same control infrastructure to handle both data validation and sequence optimization, thereby reducing overall circuit complexity while maintaining computation efficiency.
Solution Approach 2:
The sequencing circuit is designed to perform multiple functions: it validates data elements, determines optimal transmission sequences, and controls data movement. This multi-functional design eliminates the need for separate dedicated sequencing hardware, reducing circuit complexity while preserving computational efficiency through unified control architecture.
3Ease of manufacture
If data bits are transmitted in fixed sequence order, then transmission is simple, but power consumption increases due to unnecessary signal toggling
Solution Approach 1:
The system transitions from a static fixed sequence transmission to a dynamic adaptive sequence transmission. The sequencing circuit continuously monitors data values and adjusts transmission sequences in real-time based on whether consecutive data elements have identical MSBs or LSBs, thereby eliminating unnecessary signal toggling and reducing power consumption while maintaining transmission simplicity through automated control.
Solution Approach 2:
The sequencing circuit incorporates feedback mechanisms that monitor data characteristics and adjust transmission sequences accordingly. By detecting patterns in consecutive data elements and using this feedback to optimize transmission order, the system reduces signal toggling and power consumption without complicating the transmission process, as the feedback control is implemented through integrated circuit logic.
Data Source
AI summary
A circuit includes a first multiplexer configured to receive a set of data elements from a data bus, a first counter configured to output a first signal sequence, a second counter configured to output a second signal sequence, an inverter configured to output a third signal sequence responsive to the first signal sequence, and a second multiplexer configured to output a fourth signal sequence responsive to each of the first through third signal sequences. Responsive to the fourth signal sequence, the first multiplexer is configured to output bits of alternating data elements of the set of data elements in alternating sequential orders.